Hello experts,
Hirain reported an issue with an abnormal Core to Core interrupt register in IPCF. I've also reproduced this issue and want to confirm whether it's a bug in the MSCM module.
Software version: S32G_IPCF_4.10.0 D2405
Reproduce steps: M7_3 writes to the IRCP0IGR1 to trigger an interruot to A53_0. IRCP0ISR1 shows the initiating core is A53_0 instead of M7_3. I also test M7_3 writes to the IRCP0IGR2 to trigger an interruot to A53_0. IRCP0ISR2 shows the initiating core is A53_0 instead of M7_3.
And it seems that the error only occurs when M7_3 triggers an interrupt to A53_0. Please help confirm whether this is a bug in the S32G MSCM module. Thanks.
BR
MP
Hello @BogdanB
Thanks for your support. Customer has realized that this is a misunderstanding about S32G3RM.
BR
MP
@Maolin_Pan is the feedback clear or more details are needed ?
Please if clear click on "accept solution"
Hi,
Based on the S32G3 Reference Manual, this behavior is expected and not indicative of an issue. It relates to how the MSCM (Miscellaneous System Control Module) handles read/write operations.
They are read/write with variable from M7 (I assume as they are using Lauterbach), and M7 is not configure as trusted core by default so they will return as 0x00000001.
Please check chapter 8.4.19 Interrupt Router CPa Interruptb Status (IRCP0ISR0 - IRCP11ISR13), from there I also took the picture.
If you need more details or clarification please let me know and we can schedule a call.