Hi team,
The customer EVTECH reported an issue related to the ADC High-Speed enablement.
The customer is using RTD 2.0.1 and the corresponding S32K3xx RM is Rev.5 or Rev.6.
It clearly state that 0x03 (11b) is the correct setting for AMSIO[HSEN] bit. This is also supported by internal communication in ARTD-15057, where 0x03 is explicitly mentioned for higher ADC clock frequencies.
But it looks like the recommended configuration for the ADC AMSIO[HSEN] field has changed starting with S32K3 RM Rev. 7, where the value 0x01 is now used to enable High-Speed mode and added a new bit AMSIO[CMPCTRL0] to control this feature also. However, this change is not mentioned in the Rev. 7 release notes.
The corresponding RTD code also can reflect this difference of the High-Speed setting:
RTD 2.0.0 and 3.0.0
RTD 4.0.0 and 5.0.0
Hi @ZhengLin ,
From RTD view, SW team followed RM that suggested for that version. I think you should put this question to design team. They can provide the reason for that change and how it affect to this feature.
Best regards,
Nhi
Hi Nhi,
Understand that the customer should use the latest RTD version and not to modify the RTD driver by themselves. Now the question is that if the customer would like to use the RTD 2.0.1 version, whether they can still use the default RTD 2.0.1 driver code to realize the correct configuration of the High-Speed setting.
Best Regards,
Zheng Lin
Hi @ZhengLin ,
I checked silicon for version 200->300 and from 400->600, there is no difference. So, seems RTD driver just updated that based on RM updated (from Rev3(RTM201)/Rev6(RTM300) to Rev8(RTM400)).
The ticket updated ADC driver is: https://jira.sw.nxp.com/browse/ARTD-96768
There is a note:
We always recommend the customer uses the latest version. For now, RTM600 is latest version.