Hello NXP Team,
Due to specific reasons, we are still using RTD version 2.0.1 for our project on the K312。 I noticed discrepancies regarding the ADC Clock configuration for highest conversion speeds between the User Manuals from 2022 and 2025.
I have two specific questions regarding this:
- For the HSEN bit in the AMSIO register, which value should I set to enable High Speed mode in our RTD 2.0.1 context? Should it be set to 1 or 3?
- The 2022 manual does not describe or provide configuration guidance for the CMPCTRL0 bit. Do I need to explicitly configure the CMPCTRL0 bit to achieve the highest conversion speeds using High Speed ADC mode? If configuration is necessary, would it be sufficient to modify the Adc_Sar_EnableHighSpeed() function accordingly?
Thank you for your support!
Dear Pavel,
Thank you for your support. That has resolved my question.
Best regards,
Jianjie
Hello @jianjie ,
I have received feedback from our application team. The ADC clock configuration has evolved over time and both settings are valid.
That said, we do not recommend modifying the RTD driver manually. To ensure correct behavior and compatibility, it is always advised to use the latest available RTD package, which incorporates the most up-to-date configuration logic.
Best regards,
Pavel
Hello @jianjie ,
Thank you for your interesting query and for sharing your observations regarding the ADC AMSIO HSEN configuration.
I have reviewed your comments and can confirm the discrepancies you noted between the different versions of the Reference Manual. Please be informed that your query is currently being investigated internally. I will keep you updated as soon as further information becomes available.
Thank you for your patience and understanding.
Best regards,
Pavel