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Hi:
customer use case: multicore , single image . multicore share the same code and data area.
questions:
for this use case, it is needed to set the section such as 'mcal_data, mcal_bss' in each core's MPU with shareable attribution ?
because according to ARM manual , once this MPU set to shareable, it's lost cache function. and will lost a lot of performance for total application.
if RTD internal can help solved data consistency issue here, and no need to set shareable, it could be very great for performance improvment.
Please help confirmed with SW team , thanks !
Best regards
ives CHENG
Hi @Luis_Garabo ,
You means a project that uses single elf, some modules like: CAN uses 2 cores: core 0 and core 1. but PWM just use only one core 0. Then, you want to can_bss, can_data was assigned into shareable memory, but pwm_bss, pwm_data was assigned into non-shareable memory, right?
If RTD driver supports this, we will need to divide memory for all modules, like: for multiple cores used: Eth_bss_shareable, Can_bss_shareable,... and for modules just use only one core: Eth_bss_core0, Eth_bss_core 1, Can_bss_core0, Can_bss_core1,... And in linker file, we need to divide each memory region for these parts of each modules, and these memory regions were fixed with size although we don't know how much memory these modules used. Anyway, this is too complicated from my point of view.
If you want to support it in your case, you can change MemMap.h and linker file by yourself.
Best regards,
Nhi
Hi Nhi,
Thanks for the answer. Now,
What about the following. For some MCAL module which used only on 1 core, could the RTD driver provide the options to decoupled this part’s data, and let user to place in suitable sections?
For example, a multicore system where the PWM is controlled and usage is on core0, then all PWM data can be cacheable on core0.
Current RTD integrates all module’s data into MCAL_data, bss …
The suggestion is to provide a switch to generate a standalone section for each module It could be placed in BASENXP to generate a suitable memory map file.
Could this be possible?
Best Regard,
Luis
Hi @Luis_Garabo ,
For the case multiple core with single elf, you just have only one linker file as below:
mcal_bss, mcal_data are included in int_sram and you will have to set this memory region to shareable to multiple cores can access to it.
For multiple cores with multiple elf, each core uses a linker file, so mcal_data, mcal_bss is individual memory regions and you can set them to non-shareable as below:
For case 1, if you don't want to set mcal_data, mcal_bss to shareable but still want it operates in multiple cores, this means that for example if you have a variable A, in core 0, you store A to memory region of core 0, core 1 you store A to memory region core 1, but you just have 1 elf, this means that A is declared by 2 times. This is impossible from my point of view.
I don't think that RTD driver can do anything in this case, if you want to use cache, you can switch to case multiple elf.
Best regards,
Nhi