We are using an S32K310 with an external 16MHz crystal. Crystal is feeding the PLL for 120MHz out to CORE_CLK. The AIPS_PLAT_CLK is running at 60MHz. I'm trying to determine how much tolerance the UART (for LIN) baud rate will have from this arrangement. I have 50ppm of error from the crystal. I need to add jitter from the PLL to get full tolerance of the 60MHz AIP_PLAT_CLK. How do we include jitter in this AIPS_PLAT_CLK tolerance?
From there, do I use the equation below to find a baud rate tolerance % for my UART? I see in the UART section of the S32K3xx RM how to calculate baud error using SBR and OSR values. Would I simply use this equation for both Fmin / Fmax of the module clock to find my min / max baud rate?
Hi @jmnemer,
1. The formulas in 77.3.1 should be used to calculate actual baud rate, and chapter 77.3.3 should be used to estimate tolerance to baud rate mismatch. SLOW refers to when the receiver is slower than the transmitter and FAST refers to the opposite.
2. This 840ps represents the worst-case (max) jitter value. I think it is better to use the RMS value, rather than pk-pk jitter value, unless you are designing for the absolute worst-case scenario.
The RMS jitter value can be calculated as such (with +/- 7 sigma considered): 840ps/14 = 60ps.
Now, the clock at 120MHz gives a period of 8.333ns or 8333ps; meaning the jitter % can be calculated: 60ps/8333ps = 0.72%.
Adding the 50ppm tolerance (0.005%, or in your case, calculated 0.0068) gives us of 0.7268% of total tolerance, which can be used to calculate Fmin and Fmax for the AIPS_PLAT_CLK (60 MHz). However, I don't know if this can be considered as the PLL overall tolerance, so I'm going to raise a support ticket to the SW to confirm this.
I will get back with a response as soon as I get some information from the internal team.
Best regards,
Julián
Hello Julián,
Thank you for your support! I do have a few follow up questions:
1. When are the equations in 77.3.1 vs 77.3.3 expected to be used? I get quite a different value when I calculate using all 3 equations. What is significance of FAST vs SLOW?
2. How do you properly add the PLL jitter into the AIPS_PLAT_CLK tolerance? I see in the S32K3xx DS that for integer mode at 120MHz we have 353ps cycle jitter and 840ps accumulated jitter. DS states that these figures are 7sigma from RMS. How do I use these to find my actual Fmin / Fmax. I have the crystal's ~50ppm calculated to about +/-0.0068%. How do I add the jitter into this? If I simply add/subtract the 840ps to the period, I end up with poor tolerance error (> 10%). That doesn't seem correct to me. Are we expected to use the RMS value on this parameter?
Thanks!
Hi @jmnemer,
Yes. I believe your implementation is correct. Since chapter 77.3.2 & 77.3.3 does not include clock uncertainty or jitter from the clock source, you can use the baud rate formula with Fmin and Fmax values to determine the range of your baud rate, and from that, calculate the baud error %.
You must estimate the total frequency variation of the clock with crystal tolerance + PLL jitter. However, keep in mind that in the LIN driver, calculations are performed automatically assuming a fixed OSR = 16U by default.
Best regards,
Julián