When i am debug the code, SRAM_U double and single bit error flag will be set and the fault address is weird！！！ The maximum available RAM address is 0x20007000 and the fault address is bigger than that! I am so confused
Yes, of course, thank you for your answer.
best wishes!
Hi @LijieDu,
Can you create a new thread, it has nothing to do with the initial issue here.
Thank you
WOw that's it! Thanks ~
By the way, another question:
when I am doing the ram test below in startup phase, it always resets in step3, I can't find the reason,
pls help me/(ㄒoㄒ)/~~
-----------------------↓----------------↓-----------------------------------
;;RAM TEST (__RAM_START=0x1FFF9000 /__RAM_END=0x20006FFF)
;;STEP 1 - Write background 00 with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END
SUBS R2, R2, R1
SUBS R2, #1
BLE .TS1_2
MOVS R0, #0
MOVS R3, #4
.TS1_1: ;TEST STEP 1.1
STR R0, [R1]
ADD R1, R1, R3
SUBS R2, #4
BGE .TS1_1
.TS1_2: ;TEST STEP 1.1
;;STEP 2 - Verify background and write inverted background 0xFF with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END
SUBS R2, R2, R1
SUBS R2, #1
BLE .TS2_2
LDR R3, =0xFFFFFFFF
.TS2_1: ;TEST STEP 2.1
LDR R0, [R1]
CMP R0, #0
BNE Fst_RAMTSTFAIL
STR R3, [R1]
ADDS R1, R1, #4
SUBS R2, #4
BGE .TS2_1
.TS2_2: ;TEST STEP 2.2
;;STEP 3 - Verify inverted background 0xFF and write background 0x00 with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END
SUBS R2, R2, R1
SUBS R2, #1
BLE .TS3_2
MOVS R4, #0
.TS3_1: ;TEST STEP 3.1
LDR R0, [R1]
LDR R3, =0xFFFFFFFF
CMP R0, R3
BNE Fst_RAMTSTFAIL
STR R4, [R1]
ADDS R1, R1, #4
SUBS R2, #4
BGE .TS3_1
.TS3_2: ;TEST STEP 3.2
;;STEP 4 - Verify background 0x00 and write inverted background 0xFF with addresses
....
;;STEP 5 - Verify inverted background and write background with addresses decreasing
....
Hello @LijieDu,
Please close the Memory and Variable views that are currently monitoring the SRAM.
Regards,
Daniel
Yes, I have disabled the EIMCR[GEIEN] in the erm handler function.
By the way, When I just run the code without debug, it can run normal, but with debug tools and debug the code, it always generate the ram ecc fault, or just pause the code and continue to run it , will generate the fault too.
Hello @LijieDu,
Do you disable the error injection in the ERM interrupt?
EIMCR[GEIEN] = 0.
In the SRAM_U region, there is the Stack located.
The EIM must be disabled before the Stack is read.
Regards,
Daniel