2133936_en-US

[#1]

RT1176 SFPD QSPI IS25LP064D-JKLE

I am attempting to flash a custom RT1176 board that implements FlexSPI1 in the same manner as the eval board, except I have supplied flash VCC with 3.3V to support the IS25LP064D-JKLE I am trying to use. I have attached my flexspi_nor_config.c and memory setup. I am using the default flexspi_nor_polling_transfer_cm7. When I debug with Link Application to RAM Enabled, it returns "Program data - read out data value incorrect !" (line 125). I have yet to figure out what the issue is in my configuration. I am currently using an MCU Link MR, but also have access to a Jlink. My custom board has DIP Switches, and I have bootmode 1 set to 1 and bootmode 0 set to 0.

Re: RT1176 SFPD QSPI IS25LP064D-JKLE

Hi @AnteoJ ,

Thanks for your interest in NXP MIMXRT series!

The flash used by the RT1020-EVK happens to be ISSI_IS25LP064A, so you can find the corresponding flexspi_nor_config.c in its SDK . Please check this first.

Also, when replacing the flash you can first pass the tests of the built-in templates in SEC/MCUBootUtility, which are able to shield your own flash from LUT issues.

Best regards,
Gavin

Re: RT1176 SFPD QSPI IS25LP064D-JKLEI have gone through and replaced values for my specific flash according to the datasheet although I still run into a IMPRECISERR and UNDEFINSTR when I start up debug. I am not sure if there are additional parameters that need to be adjusted. Here is my code so far: /*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#include "evkbmimxrt1170_flexspi_nor_config.h"

/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif

/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif

#define FLASH_DUMMY_CYCLES 0x03
#define FLASH_DUMMY_VALUE 0x03

const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption = 0x10,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = 8u * 1024u * 1024u,
/* Enable flash configuration feature */
.configCmdEnable = 1u,
.configModeType[0] = kDeviceConfigCmdType_Generic,
/* Set configuration command sequences */
.configCmdSeqs[0] =
{
.seqNum = 1,
.seqId = 12,
.reserved = 0,
},
/* Prepare setting value for Read Register in flash */
.configCmdArgs[0] = (FLASH_DUMMY_VALUE << 4),
.lookupTable =
{
// Read LUTs
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x20),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04),

// Read Status LUTs
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),

// Write Enable LUTs
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),

// Erase Sector LUTs
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),

// Erase Block LUTs
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),

// Pape Program LUTs
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),

// Erase Chip LUTs
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),

// Set Read Register LUTs
[4 * 12 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xC0, WRITE_SDR, FLEXSPI_1PAD, 0x01),
[4 * 12 + 1] = FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x00, 0, 0, 0),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = 0x1,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */