Hello NXP Community
I’m using the CLRC66301B NFC reader IC and trying to activate Power-down mode by driving the PDOWN pin high (3.3 V), as specified in the datasheet. However, the current draw remains at 2 mA, while the datasheet indicates it should be between 8 nA and 40 nA in power-down.
Setup Details:
PDOWN pin: 3.3 V (constant high)
VDDs: VDD(TX), VDD(AUX), VDD(MCU) all at 3.3 V
Interface: I²C (idle during test)
XTAL: 27.12 MHz crystal connected
No communication or activity during current measurement
Measured current: ~2 mA
Questions:
1. Are any register configurations required before asserting PDOWN?
2. Could IRQ, XTAL, IFSEL, or other GPIOs prevent entry into true power-down mode?
3. Does PDOWN require additional timing or sequencing with VDD or reset?
Any insights or suggestions would be appreciated.
Thanks,
Umasankar
Hi,
When you mention that current consumption is reduced when SDA and SCL are physically disconnected, does it mean that you are removing all connections on this pin (removing both Host MCU and pull-up resistors), or is it that those lines are only disconnected from the Host MCU?
Also, could you please describe the method, equipment and test point you are using for the measurement?
Regards,
Eduardo.
Dear NXP Team,
I conducted power-down current testing using the official CLEV6630ARD board with the CLRC66303B chip. The current reaches ~40 nA only when SDA and SCL are physically disconnected before any I²C communication. If I²C is used even once, current remains above 2 mA, even after asserting PDOWN high.
Could you please clarify what should be done with the I²C lines before entering PDOWN? Specifically:
Should the MCU set SDA and SCL to high-impedance (input, no pull) before asserting PDOWN?
Does any prior I²C communication prevent the chip from entering true hard power-down?
Thank you.
Dear NXP Team,
I previously raised a query regarding hard power-down current with the CLRC66301HN, and your response recommended migrating to the CLRC663 Plus family (CLRC66303). I have since switched to CLRC66303B, using a custom board based on the CLEV6630ARD reference design, and I would like to follow up with updated test results.
Your earlier reply focused on LPCD behavior and AN11783, but this issue concerns only hard power-down via the PDOWN pin, with no RF field or LPCD active.
Power-Down Current Measurements (CLRC66303B):
>When PDOWN is LOW (chip active, RF field on): ~100 mA
>When PDOWN is HIGH and I²C pull-ups are present: ~1.2 mA
>When PDOWN is HIGH and I²C lines are driven LOW: ~6.6 mA
>When PDOWN is HIGH and I²C lines are physically disconnected before any use: ~40 nA
Only when SDA and SCL are physically disconnected before any I²C communication does the chip draw ~40 nA in PDOWN. If I²C is used even once, current remains high even after PDOWN is asserted HIGH.
Hardware Setup Summary:
Chip: CLRC66303B, I²C mode.
MCU: TI CC2652R7, 100 kHz I²C
Voltage: 3.3 V regulated
Pull-ups: 4.7 kΩ to 3.3 V on SDA/SCL
Unused pins: Pulled as per datasheet
No RF or LPCD features enabled
Schematic design: Based on CLEV6630ARD (attached)
Questions for Clarification:
1. Are SDA/SCL internally biased during PDOWN mode?
2. Does any prior I²C activity prevent true power-down, even if PDOWN is later set HIGH?
3. Is it necessary to set MCU I²C pins to Hi-Z (input, no pull) before asserting PDOWN?
4. Is there an NXP-recommended method to reliably achieve <100 nA in hard PDOWN mode without physically disconnecting I²C lines?
We aim to ensure battery longevity and must achieve the datasheet-stated low-power behavior. Any guidance or documentation specifically about PDOWN behavior and I²C leakage would be greatly appreciated.
Schematic is attached for reference.
Best regards,
Umasankar C
Hello @Umasankarc
Hope you are doing well.
I understand you are using a custom board based on CLRC66301HN (non-plus), is this correct? If so, please consider that we recommend using the CLRC663 plus family (CLRC66303) instead.
HIGH level on pin PDOWN should enable a hard power-down. Power-down current (Ipd) stated in the Data Sheet corresponds to the sum of all supply currents in CLRC663 chip; however, additional power might be consumed by external components embedded in the board.
Some recommendations for a low power design are described in AN11783 CLRC663 plus Low Power Card Detection, Section 3.4.
Regards,
Eduardo.