Hi Team,
The RM describes the procedure to initialize SRAM ranges in the following way:
The mapping rule descripte here is 1 -> 64-byte(0x40)
The shown bitwise operation is performed to define the ranges in the PRAMIAS and PRAMIAE registers. Which seems to work correctly with SRAMC, SRAMC_1, SRAMC_2 and SRAMC_3 but it does not work with STDBY_SRAM_CFG.
This has been confirmed by me and the customer, they were traying to initialize the 32K of STDBY_SRAM, using the calculation in the RM they had:
PRAMIAS = 0
PRAMIAE = 0x1FF
but only the range 0-0x1FF0 (8K) was initialized.
And when they used PRAMIAE = 0x7FF, the complete range was initialized.
So the actual mapping rule for Standby SRAM is 1 -> 16byte(0x10)
I found 0x7FF defined in the https://github.com/nxp-auto-linux/arm-trusted-firmware/blob/c9a7f81230064d21e403cfc315cbd3ffdc18752f...
#define SSRAM_MAX_ADDR 0x7FF
My question is:
- For the Standby SRAM mapping rule, which document have this description? if you know please kindly provide the information with me. Thanks.
- With the name MAX ADDR I would expect it to be the the max offset of the Standby range, which is 0x7FFF(32KB), if it is possible add a comment or modify the definition name so it is not confusing?
BRs,
Tianxiang
Hi Tianxiang,
Unfortunately, we don't have any such documentation. You need to ask someone from hardware for this. I saw that the validation team uses this forumula which seems to work for this case: https://bitbucket.sw.nxp.com/projects/AMPFVAL/repos/auto-fval/browse/validation/sramc/driver/inc/sra... . I am not sure if that's the correct one. We talked with people from the hardware teams in order to get the correct settings for SRAM/SSRAM initialization.
Regarding the name of SSRAM_MAX_ADDR, I am not sure if we would rename it. It is only used once and it is given as a parameter to: clear_sramc_range which has its parameters named as offsets so it implies it is not exactly the address (different from clear_sram_range).
Best regards,
Andrei