Hi All,
I am trying to import a "lpcxpresso54s018_hello_world_qspi_xip" to my custom board. But I got an error message "File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address." . The goal is to upload an image to the EXT SPI FLASH and the MCU will boot from the EXT SPI FLASH.
Can anyone please give an advice on how to fix the issue?
Error Message:
Executing flash operation 'Program' (Program file into flash: lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin) - Mon Jun 16 10:48:33 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004/Debug\LPC54S018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:000f:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Boot ROM stalled - at read watch #1 address 0x40000040
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54S018
DAP stride is 4096 bytes (1024 words)
( 65) Chip Setup Complete
Connected: was_reset=false. was_stopped=true
( 70) License Check Complete
File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address.
(100) Target Operation Failed
Unable to perform operation!
Command failed with exit code 1
Thanks,
6/16/2025
Hi Harry,
Thanks for your advice on the PIO0_4,5,6!
Although I am unable to see the "hello world" message in the "lpc54018iotmodule_led_blinky_Custom Board 000", I followed your instruction on PIO0_4,5,6, and I am able to run the "lpcxpresso54s018_led_blinky_lpc_blinky_Custom Board 000". I also disconnect the SWD and power on the custom board and the blink still on going, this should be enough to proof the SPI BOOT is working right?
How do I view the "Hello World" message for the "lpc54018iotmodule_led_blinky_Custom Board 000" project?
For the PIO0_4,5,6, if I set it to all high so it should be in auto-boot mode, I wonder why it will prevent from uploading .bin file to the SPI NOR FLASH?
Also, can I use the MCU-LINK PRO and the MCUExpresso IDE for production programming?
Thanks,
7/25/2025
Hi @mtsang
I got some new idea from our internal team.
You can check the ISP pins, to ensure that the chip boot type is SPIFI flash boot.
And they suggest to refer to the AN12122 .
You can use lpcxpresso54s018_hello_world_qspi_xip this demo.
BR
Harry
Hi Harry,
Thank you so much for your help and please give me an update if you got a result from the internal team. How soon will I hear back from you or the internal team?
Can you think of any other part of the schematics/code that will cause the board to be able to upload/erase code to the SPI NOR Flash but not able to boot and debug? I will double check base on your suggestion.
Currently I am using "lpc54018iotmodule_hello_world" example.
Thanks,
7/15/2025
Hi @mtsang
I think this may be due to an incorrect SPI Descriptor, but unfortunately, I don't have a flash chip(IS25LP128F-JBLA3) on hand, so i can not test it, i will seek help from internal team.
I will inform you as soon as there is a result. Thanks for your understanding.
BR
Harry
Hi Harry,
I can't debug the unit. It has below error output.
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869)
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:0009:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Waiting for target to stop...
Warning - processor did not halt - gave up waiting
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Sending SYSRESETREQ to run flash driver
rst - Boot ROM stall address was not accessed (but we entered debug on VectorCatch anyway)
There was a problem after we succesfully downloaded flash driver code to the target, so we are going to compare the flash driver code with the memory where it was loaded.
Note that, after driver initialization, some difference is normal in 'generic' drivers.
Driver from AXF file:
//------------------
//Flash Data
//------------------
AFTER driver startup timeout (302 5ms retries)
Driver Addresses
Start: 00000000
Entry: 0000009D
End: 0000128C
Stack: 00002290
Mailbox:0000A290
Driver Register State
R0: 00000000
R1: 200273F8
R2: 0300AF21
R3: 00000000
R4: 40000000
R5: 00000000
R6: 00000000
R7: 00000000
R8: 00000000
R9: 00000000
R10: 00000000
R11: 00000000
R12: 00000000
SP: 00002288
LR: 0300BBA5
PC: 0300BDF2
xPSR: 21000000
MSP: 00002288
PSP: 00002290
CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1)
Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash.
chip initialization failed - Ef(34): Timed-out initializing flash.
failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx
I click on "Attach to running target using Link server", and there what I got:
I clicked on the "Verify Only" in the GUI Flash Tool and it seems to be able to download the .bin file to the SPI NOR Flash
Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Mon Jul 14 15:05:56 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:0009:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Waiting for target to stop...
Warning - processor did not halt - gave up waiting
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Using SOFT reset to run the flash driver
rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway)
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
( 65) Chip Setup Complete
Connected: was_reset=false. was_stopped=false
( 70) License Check Complete
Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4
Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident)
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
( 0) Comparing Flash against file at 0x10000000
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
(100) File matches flash.
Read 0x3BA4 bytes in 43ms (about 355kB/s) - verify succeeded
Thanks,
7/14/2025
Hi @mtsang
Can you debug successfully?
BR
Harry
Hi Harry,
I used the SPIFI descriptor you posted, but still it has the same problem.
I got the following error message after I clicked on "Debug with Linkserver Probes"
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869)
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:0014:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Boot ROM stalled - at read watch #1 address 0x40000040
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
SYSRESETREQ reset omitted - already reset
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
Connected: was_reset=false. was_stopped=true
Awaiting telnet connection to port 3330 ...
GDB nonstop mode enabled
Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident)
Retask watch 0
Sending SYSRESETREQ to run flash driver
Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1)
AFTER driver startup timeout (302 5ms retries)
Driver Addresses
Start: 00000000
Entry: 0000009D
End: 0000128C
Stack: 00002290
Mailbox:0000A290
Driver Register State
R0: 0000A290
R1: 00000000
R2: 00000000
R3: 00000000
R4: 00000000
R5: 00000000
R6: 00000000
R7: 00000000
R8: 00000000
R9: 00000000
R10: 00000000
R11: 00000000
R12: 00000000
SP: 00002290
LR: 0000009D
PC: 000000A0
xPSR: 61000000
MSP: 00002290
PSP: 00002290
CFBP: 00010001 (CONTROL=0x0, FAULTMASK=0x1, BASEPRI=0x0, PRIMASK=0x1)
Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash.
(100) Writing Flash ended with an error.
Target error from Commit Flash write: Ef(34): Timed-out initializing flash.
GDB stub (C:\nxp\LinkServer_24.12.21\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.
Thanks,
7/10/2025
Hi @mtsang
If you want to XIP.
Did you try to change to it in startup_lpc54s018.c?
#ifdef IS25LP128F-JBLA3
/* SPI Descriptor - IS25LP128F-JBLA3 */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr
(void (*)(void))0x0018609D, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x1301001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
(void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endifBR
Harry
Hi Harry,
Thanks for the schematics correction! However it seems like I am able to flash the .bin file to the SPI NOR Flash, but the MCU is not able to boot from the SPI NOR Flash. I installed and removed PIO0_6 pull-up resistor but it didnt help.
Flash the SPI NOR FLASH
Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Wed Jul 09 16:39:19 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:000b:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Waiting for target to stop...
Warning - processor did not halt - gave up waiting
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Using SOFT reset to run the flash driver
rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway)
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
( 65) Chip Setup Complete
Connected: was_reset=false. was_stopped=false
( 70) License Check Complete
Loading 'lpc54018iotmodule_hello_world_lpc54018iotmodule.axf' ELF 0x10000000 len 0x3BA4
Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident)
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
Writing 15268 bytes to address 0x10000000 in Flash
1 of 1 ( 0) Writing sectors 0-0 at 0x10000000 with 15268 bytes
( 0) at 10000000: 0 bytes - 0/15268
(100) at 10000000: 65536 bytes - 65536/15268
Sectors written: 0, unchanged: 1, total: 1
Erased/Wrote sector 0-0 with 15268 bytes in 30msec
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
(100) Finished writing Flash successfully.
Flash Write Done
Loaded 0x3BA4 bytes in 89ms (about 171kB/s)
Reset target (romstall)
Starting execution using system reset with a stall address
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1)
Stopped (Was Reset) [Reset from Unknown]: Watchpoint (Temp) #1 - read watchpoint at 0x40000040 Data watch for bootloader stall
restart on reset
Verify the SPI NOR FLASH's content
Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Wed Jul 09 16:43:17 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:000b:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Boot ROM stalled - at read watch #1 address 0x40000040
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
( 65) Chip Setup Complete
Connected: was_reset=false. was_stopped=true
( 70) License Check Complete
Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4
Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident)
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000)
( 0) Comparing Flash against file at 0x10000000
Closing flash driver LPC540xx_SPIFI_SFDP.cfx
(100) File matches flash.
Read 0x3BA4 bytes in 41ms (about 372kB/s) - verify succeeded
Thanks,
7/9/2025
Hi Harry,
I am terribly sorry I didn't check the SPI NOR Flash pin out. Thanks for your catch!!! I used jumper cable to fix the problem for now.
Seems like I am able to program and mass erase the custom board right now. At least it didnt show any error message.
I am using "lpc54018iotmodule_hello_world_virtual_com_xip" as an example. Is there anything I can do to verify the SPI boot function? Also where the "HELLO WORLD" message will shows up?
Thanks a lot!
7/8/2025
Hi @mtsang
I think your schematics of the SPI NOR FLASH is wrong.
In the NOR FLASH Data sheet.
PIN 5 SI should be connected IO0.
PIN 2 SO should be connected IO1.
But in your schematic.
PIN 5 SI is connected IO1.
BR
Harry
Hi Harry,
Sure! Attached is the schematics of the SPI NOR FLASH.
SPIFI_CSN -> LPC54S018JET180E_N7
SPIFI_IO0 -> LPC54S018JET180E_M7
SPIFI_IO1 -> LPC54S018JET180E_K8
SPIFI_IO2 -> LPC54S018JET180E_M9
SPIFI_IO3 -> LPC54S018JET180E_L9
SPIFI_SCK -> LPC54S018JET180E_M13
Thanks,
7/7/2025
Hi @mtsang
Can you share your schematic about the flash?
BR
Harry
Hi Harry,
Thanks for your detailed response, but I am still getting the same error.
Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Thu Jul 03 14:29:23 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:001a:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Waiting for target to stop...
Warning - processor did not halt - gave up waiting
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Using SOFT reset to run the flash driver
rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway)
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters.
Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF)
chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters.
failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx
( 65) Chip Setup Complete
(100) Target Operation Failed
Unable to perform operation!
Command failed with exit code 1
Thanks,
7/3/2025
Hi @mtsang
About the different register define.
I think you can refer to the UM11060 Table 12. Image header for the LPC540xx devices.
I checked the IS25LP128F-JBLA3 DATA SHEET.
Regarding how to configure relevant parameters, let me give an example to illustrate.
1.
So setStatusFxId is 0B.
2.
So setOptionsFxId is 0F
3.
So the getReadCmdFxId is 0x11.
4.
So getStatusFxId is 06.
And so on.
And i write one based on the IS25LP128F-JBLA3 data sheet and the SDK startup_lpc54s018.c
#ifdef IS25LP128F-JBLA3
/* SPI Descriptor - IS25LP128F-JBLA3 */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr
(void (*)(void))0x0018609D, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x1301001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
(void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endifYou can double check.
And then
You can replace it with IS25LP128F-JBLA3.
BR
Harry
Hi Harry,
Sorry for the late reply and thanks for the infos.
I am still confused about how to find the info marked with BOLD Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.
Also for the macro marked with BOLD text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc)
What I found so far, please double check if I am correct
//maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
Clock Frequency except for fast read: 166Mhz (A3h)
Clock Frequency for read (03h): 80Mhz (50h)
#ifdef IS25LP128F-JBLA3
/* SPIFI Descriptor - IS25LP128F-JBLA3 */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x0018609D, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // extid 4-7
(void (*)(void))0x0001001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // subBlks + subBlkSize
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif
Thanks,
6/30/2025
Hi Harry,
Sorry for the late reply and thanks for the info.
However I am still confused about how to find the info marked with Red Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.
Also for the macro marked with blue text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc)
Here's what I found, please double check if they are correct:
//maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
Clock Frequency except for fast read: 166Mhz (A3h)
Clock Frequency for read (03h): 80Mhz (50h)
#ifdef IS25LP128F-JBLA3
/* SPIFI Descriptor - IS25LP128F-JBLA3 */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x0018609D, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // extid 4-7
(void (*)(void))0x0001001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // subBlks + subBlkSize
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif
Thanks,
6/30/2025
Hi @mtsang
You are right. You need to modify the SPIFI Descriptor.
You currently have:
(void (*)(void))0x001870EF, // mfgId + extCount
This corresponds to:
mfgId = 0xEF (Winbond, not correct for IS25LP128F)
device ID = 0x70 (part of JEDEC ID for W25Q128)
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
BR
Harry
Hi Harry,
Thank you so much for the reply!
I am using "IS25LP128F-JBLA3" for the custom board. According to the datasheet(please see attached IS25LP128F-JBLA3 datasheet), it seems to support SFDP. I am switching back to "LPC540xx_SPIFI_SFDP.cfx" for memory config.
I checked the "SPIFI Descriptor" in the "LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip" startup_lpc54018.c
I saw the SPIFI Descriptor :
#ifdef W25Q128JVFM
/* SPIFI Descriptor - W25Q128JVFM */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x001870EF, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // extid 4-7
(void (*)(void))0x0001001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // subBlks + subBlkSize
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif
Should I change the SPIFI Descriptor(I modified the Bold Text)? Also I am unsure what to change for the under-line section. What else I need to change in order to make the example project works on my custom board:
#ifdef IS25LP128F-JBLA3
/* SPIFI Descriptor - IS25LP128F-JBLA3 */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x001870EF, // mfgId + extCount
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // extid 4-7
(void (*)(void))0x0001001D, // caps
(void (*)(void))0x00000100, // Blks + RESV1
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // subBlks + subBlkSize
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif
Thanks,
6/23/2025
Hi @mtsang
From your log:
Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters.
The SPIFI flash driver attempted to probe your external flash device via SFDP, but failed to identify valid parameters for your flash.
What is the exact part number of the flash IC on your custom board?
Check its datasheet for SFDP support — not all parts provide SFDP data.
BR
Harry
Hi Harry,
I deselect the "Link Application to RAM" and I got the below error message:
Executing flash operation 'Program' (Program file into flash: Debug\lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003.axf) - Tue Jun 17 12:17:21 PDT 2025
Checking MCU info...
Scanning for targets...
Executing flash action...
LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869)
( 0) Reading remote configuration
Wc(03). No cache support.
Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003/Debug\LPC54S018.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: F4ON0DG121ZHK
VID:PID: 1FC9:0143
USB Path: 0001:0018:00
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall
Waiting for target to stop...
Warning - processor did not halt - gave up waiting
( 30) Emulator Connected
( 40) Debug Halt
( 50) CPU ID
debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info:
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
NXP: LPC54S018
DAP stride is 4096 bytes (1024 words)
Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx
Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01'
Opening flash driver LPC540xx_SPIFI_SFDP.cfx
Using SOFT reset to run the flash driver
rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway)
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters.
Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF)
chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters.
failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx
( 65) Chip Setup Complete
(100) Target Operation Failed
Unable to perform operation!
Command failed with exit code 1
Thanks,
6/17/2025
Hi @mtsang
I have a question.
According to your need.
Why you select the "link application to ram"
You can deselect this, and try again.
BR
Harry