I want to send 120 bytes via UART1 with an i.MX RT1060 (MIMXRT1061CVJ5B) using the FIFO. I've set the TX FIFO to 256 bytes, but it's not working. Is this a processor bug?
Hello,
As I said, I can't do anything with these bloated examples,
because I need complete control over the module,
and many important functions aren't included in the API.
But I was able to solve it after all:
an important control bit "DREQ" wasn't set:
Now it's running like crazy
It's a great machine, but the API is completely inadequate...
Thanks for your effort.
Regards, Mark
Hi @Mark16 ,
Thanks for your reply.
Wish it helps you.
If you still have question about it, please kindly let me know.
Wish you a nice day!
Best Regards
MayLiu
Hello,
I'm not confused.
I just want to send 120 bytes over UART1 every 100ms,
with minimal overhead, i.e., without interrupts, etc.
With a 256-byte FIFO, this would be super easy.
With a 4-byte FIFO, it won't work without interrupts or polling.
I've been trying to solve it with the famous eDMA for 5 days now,
but I've completely failed.
I've read the relevant chapters in the manual several times,
but a lot remains unclear.
The example programs in the SDK and the drivers in "fsl_lpuart_edma,"
"fsl_edma," etc., are incredibly bloated, deeply nested,
and can only be used in a specific way.
They're useless for simple, straightforward applications.
I have 25 years of professional experience as an embedded programmer,
with a wide variety of processors,
but I've never experienced anything like this.
Please explain to me how to set the registers for UART1 and eDMA to easily send 120 bytes over UART1.
Please use "bare metal" style, e.g.:
LPUART1->CTRL = ?
etc...
DMA0->SERQ = ?
etc...
DMA0->TCD[0].SADDR = ?
etc...
Hi @Mark16 ,
Thanks for your reply.
The LPUART FIFO size of the RT1060 processor is also 16 bytes. Could you share with me the application requirements for a larger FIFO size? and could you tell me your point of confusion? I can forward your requirements to the NXP internal team.
You mentioned that "using LPUART + DMA " is also an effective transmission method. The NXP SDK demos have a lot of examples for you to use.
Best Regards
MayLiu
That's a bit disappointing.
Now they've built this mega-machine,
with amazing features,
and then they're skimping on the UART FIFO.
Why is that?
Even my old LPC2478 had a larger UART FIFO of 16 bytes.
I want my money back
Then I guess I'll have to pump the data via eDMA...
Hi @Mark16 ，
Thanks for your updated information.
LPUART TXFIFOSIZE/RXFIFOSIZE size is fixed, you can not modify it.
The value in RXWATER and TXWATER must be set to be less than the receive FIFO/buffer and transmit buffer/FIFO size, it means the value in RXWATER and TXWATER must be set to be less than 4 datawords.
Best Regards
MayLiu
Where can i set the value?
In the Config Tool?
In the Config Tool?
Hi @Mark16 ,
Thank you so much for your interest in our products and for using our community.
Question: I want to send 120 bytes via UART1 with an i.MX RT1060 (MIMXRT1061CVJ5B) using the FIFO. I've set the TX FIFO to 256 bytes, but it's not working. Is this a processor bug?
Answer:
This is not a processor bug.
In IMXRT1060RM, The maximum number of transmit/receive datawords that can be stored in the TXFIFOSIZE/RXFIFOSIZE.
https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM&location=null
I run a SDK demo on MIMXRT1060-EVK board for you to better understand.
The LPUART RXFIFOSIZE / TXFIFOSIZE value are 4 datawords. The value in RXWATER and TXWATER must be set to be less than the receive FIFO/buffer and transmit buffer/FIFO size
The value you set the TX FIFO to 256 bytes are not correct value, Please set the value based on the MIMXRT1060RM.
Wish it helps you.
If you still have question about it, please kindly let me know.
Wish you a nice day!
Best Regards
MayLiu