2078684_en-US

[#1]

[Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Hi Team,

Customer Veoneer (working on Comet projects), is having issues running BIST and eMcem on S32K388 device using SAF 1.0.5. They are running BIST, which is completing with the STCU registers indicating that all of the tests are finishing; however the device is not doing a functional reset afterwards, it is doing a destructive reset. Also, after this reset and performing eMcem init, the MCU encounters a hard fault. After checking the FCCU registers, these point to faults in NCF[0] and NCF[2]. Looking into DCM_GPR registers, these NCF flags translate to be the following errors:

• CM7_0_LOCKUP
• PRAM0_ECC_ERR
• CM7_2_ITCM_ECC_ERR

We had debug calls with them to check and they have a configuration that follows all pre-requisites outlined in the UM for BIST, and couldn’t locate any immediate issues that could be causing the faults after eMcem init. Can you support and check what is missing and/or causing the BIST to trigger a destructive reset instead of the functional reset, and also if there’s any setting in their configuration that could be leading to the faults?

I’m attaching SFR dump with their faults’ register information and their Tresos configuration. Here’s also a code snippet with the state machine they programmed to run and call BIST APIs and check for pre-conditions:

NO_OPTIMIZE FUNC(void, SafetyMgr_CODE) SafetyMgr_Bist_Run (void)
{
   Bist_StatusType bist_status = BIST_OK;
   Std_ReturnType return_val = E_OK;

   //SafetyMgr_Bist_PreconditionCheck();

   /* Bist startup if the precondition are met */
   //if ( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK)
   //{
      bist_status = Bist_GetExecStatus(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support
      switch (bist_status)
      {
      case BIST_BUSY:
         /* Timeout monitor */
         safetymgr_bist_check = SAFETYMGR_BIST_CHK_TIMEOUT;
         break;

      case BIST_NORUN:
         /* Start Bist test */
         SafetyMgr_Bist_PreconditionCheck();
         if( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK)
         {
            return_val = Bist_Run(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support
            if (return_val == E_NOT_OK)
            {
               safetymgr_bist_check = SAFETYMGR_BIST_CHK_TEST_NO_SUPP;
            }
         }
         break;

      case BIST_INTEGRITY_FAIL:
         /* Start Bist test */
         SafetyMgr_Bist_PreconditionCheck();
         if( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK)
         {
            return_val = E_OK; //Bist_Run(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support
            if (return_val == E_NOT_OK)
            {
               safetymgr_bist_check = SAFETYMGR_BIST_CHK_TEST_NO_SUPP;
            }
         }
         SET_SWTP4();
         break;

      case BIST_ERROR:
         safetymgr_bist_check = SAFETYMGR_BIST_CHK_ERROR;
         bist_error = Bist_GetRawErrorStatus(); //To Do: Re-enable after SAF package is updated for S32K388 support
         SET_SWTP2();
         break;

      case BIST_FAILED:
         safetymgr_bist_check = SAFETYMGR_BIST_CHK_FAILED;
         bist_ret_val_RD = Bist_GetFailRDs (bist_LBistRDList, bist_MBistRDList); //To Do: Re-enable after SAF package is updated for S32K388 support
         SET_SWTP3();
         break;
      
      default:
         /* bist_status is BIST_OK --> run of selected BIST sequence was successfully proceed without any faults */
         safetymgr_bist_check = SAFETYMGR_BIST_CHK_NO_FAIL;
         SET_SWTP4();
         break;
      }
   //}
   //else
   //{
      /* Precondition not met */
   //}
   //IP_MC_ME->MODE_CONF &= ~0x02; //Clear the functional reset
   //IP_MC_ME->MODE_UPD = 0x00; //update mode
   SET_SWTP5();
}

/******************************************************************************
* details
*     This function ensures that all preconditions are met before starting the Bist
* param[in]
*     none
* param[in]
*     none
* param[out]
*     none
* param[out]
*     none
* return
*     none
* constraints
*     <>
* invocation_criteria
*     <>
******************************************************************************/
NO_OPTIMIZE FUNC(void, SafetyMgr_CODE) SafetyMgr_Bist_PreconditionCheck (void)
{
   /* Bist preconditions */
   /* 1. Only a single core should be active and used to configure the MCU for the runtime
   self-test. Core CM7_0 is the recommended core. Hence, the MCU should enter an
   operating mode which disables all other cores and to ensure no other operation is
   being carried out by CM7_0.
   2. All communication interfaces (like CAN, ENET, DSPI, FLEXRAY, I2C, etc.) need to be
   disabled.
   3. Ensure that software initiated functional/destructive resets are not triggered while
   performing self-test.
   4. All system and peripheral clocks should be configured to generate max functional
   frequency as defined in the device reference manual and data sheet.
   5. LBIST_CLK should be set to 40 MHz.
   6. The system clock should be based on PLL. */
   
   uint32 RegVal1;
   uint8 instance;
   FLEXCAN_Type * const flexcanBase[] = IP_FLEXCAN_BASE_PTRS;
   LPSPI_Type * const Lpspi_Ip_apxBases[LPSPI_INSTANCE_COUNT] = IP_LPSPI_BASE_PTRS;
   MDM_AP_Type * const mdm_ap_base[] = IP_MDM_AP_BASE_PTRS;

   VAR(uint8, FBLMGR_VAR) tctr;
	VAR(Mcu_PllStatusType, FBLMGR_VAR)  pll_status;
  
  /* Enable all clocks using alternate clock configuration */
   do
   {
      tctr = (uint8)0;
	  
	  /* Minimum MCAL Initialization */
	  /* NXP: MCU Precompile variant selected. Config parameter not required */
	  //(void)Mcu_Init(&Mcu_PreCompileConfig);

	  /* PLL Initialization */
	  /* Initialize MCU Clock*/
	  /* parameter 0 is chosen here by default, the first clock configuration */
	  (void)Mcu_InitClock(McuClockSettingConfig_1);
	  

      /* wait till PLL lock or for the timeout to expire */
      do
      {
         /* while here the PLL is unable to lock, keep waiting for it to lock
         or for the timeout to expire */
         pll_status = Mcu_GetPllStatus();
         tctr++;
      }while((pll_status != MCU_PLL_LOCKED) && (tctr < /*PLL_MAX_CHECK_STATUS_COUNTS*/ 100u));

   }while(pll_status == MCU_PLL_UNLOCKED);

	/* distribute the clock */
	Mcu_DistributePllClock();
  
	Mcu_SetMode(McuModeSettingConf_1);

   /* disable all CAN */
   for ( instance = 0; instance < FLEXCAN_INSTANCE_COUNT; instance++ )
   {
      flexcanBase[instance]->MCR |= FLEXCAN_MCR_MDIS_MASK;
   }
   safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_CAN_CHK;

   /* disable all SPI */
   for ( instance = 0; instance < LPSPI_INSTANCE_COUNT; instance++ )
   {
      RegVal1 = (Lpspi_Ip_apxBases[instance]->CR & (~LPSPI_CR_MEN_MASK));
      RegVal1 |= LPSPI_CR_RST_MASK;
      Lpspi_Ip_apxBases[instance]->CR = RegVal1;
   }

   /* ensure there is no function/destructive reset trigger */
   if( MDM_AP_MDMAPSTTS_FUNCRST(mdm_ap_base[0]->MDMAPSTTS) == 0 )
   {
      safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_FUNC_RST_CHK;
   }
   if( MDM_AP_MDMAPSTTS_DESTRST(mdm_ap_base[0]->MDMAPSTTS) == 0 )
   {
      safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_DESTR_RST_CHK;
   }
   
   IP_MC_ME->MODE_CONF |= 0x02; //set functional reset
   IP_MC_ME->MODE_UPD = 0x01; //update mode
}

Thanks,
Daniel V.

Safety_SWRe: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Hi Luke,
I don't remember exactly, but I think we have compared Tresos MCU clock settings between SAF Demo example and customers setup and found some disabled cocks needed for LBIST.

Simply you can turn on all clocks, higher freq, better and in addition you can disable all FCCU channels before BIST. Trying to avoid anything which could cause reset, so also turn off watchdogs, all external communication, PMIC WDG, other cores inactive (clock enabled but keep in reset or inactive) etc.

Kind Regards,
Radoslav

Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Hello @RadoslavB  and @dvelazquez 

May I ask about your case?

My customer is facing similar issue during BIST.

May I ask, which point was related with the issue?

(I saw that you mentioned only clock, but I would like to get more information..)

Thank you.

Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Hi Daniel,

Can we close this ticket?
I think per last debug session we have resolved the issue by correct configuration of the clocks.

Kind Regards,
Radoslav

Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Update: sent customer .elf file for the SAF BIST demo discussed in meeting (attaching as reference). The team verified it worked on our side with K388 and checked the device ID so they should have the same chip revision as the customers. 

Customer has new update, can you review:

"""

Hello, I ran into significant issues with flashing the precompiled elf files on our hardware, I am trying to correct the issues. But is there any chance that you can review this sample code? It is essentially our main, MCAL, and SAF files (everything else stripped out). With this reduced set I am still running into the issues with BIST not completing. I attached the pre-compiled binaries (under build/PrecompiledBinaries) as well as the source, make, and linker files used in our build. The .out files are just elf files. There are 3 binaries, ApplicationCore0, ApplicationCore2, and IVT. They each need to be flashed. 

They were compiled and linked using Windriver Diab 7.0.4

"""

Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues

Update:
We are currently in progress with the customer via debug calls.
Customer is trying now to execute the BIST via SAF Demo which he didn't try yet.
We are trying to find HW configuration differences which might corrupt BIST execution between the customer application and SAF Demo example.