It appears that the Watchdog driver example for RT1170 EVKB Evaluation board was setup to only work for only CM7 core.
Given a basic Dual Core application, how should I setup both CM7 and CM4 cores to implement their own Watchdog peripheral? If CM7 utilizes WDOG1 for system reset, then how should CM4's watchdog be setup to protect against an unexpected code execution malfunction? Should CM4 use WDOG3/4 or something else (EWM)?
HI @lsrbigfoot ,
Thanks for your updated information.
If you do not mind, Please create a new case for your question, for the current case is accept as solution.
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MayLiu
Thank you for response.
Can WDOG1 internally reset the CPU if MCU pins WDOG_B and WDOG_RESET_B_DEB (aka WDOG_RST_B_DEB), are not connected to anything? If yes, what steps are required to achieve this?
Next for WDOG3 and WDOG4, there appears to be up four clock source options available, but the chip-specific information does not appear to give a clear indication about what those clock sources are and what the order is for each clock source.
Am I looking at the right table? Where in IMXRT1170RM can I find what the 4 clock sources are for WDOG3 and WDOG4, according to register CS[CLK]?
Hi @lsrbigfoot ,
Thank you so much for your interest in our products and for using our community.
In IMXRT1170RM refence manual, chapter CPU Watchdog Timer (WDOG 3,4) described that
WDOG4 services the CPU reset for the CM4. WDOG3 service the CPU reset for the CM7.
WDOG1 and WDOG2 can service the CPU reset for both the CM4 and CM7.
https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM
Wish it helps you.
If you still have question about it, please kindly let me know.
BR
MayLiu