Hello Community,
I tried to initialize DDR on M7 core and will use DDR memory on both M7 and A53 core in S32G274A soc.
But I am little confused about the memory map.
According to the memory map file attached into S32G2RM (below picture), the DDR address on M7 core is mapped to 0x6000.0000 to 0xDFFF.FFFF in case of 2GB size DDR.
Is it correct?
In addition to this, if A53 core will not initialize DDR, then what is the address range of DDR in A53 side? 0x8000.0000 ~ 0xFFFF.FFFF or 0x6000.0000 ~ 0xDFFFF.FFFF(same as M7 core)?
Thanks,
Harry
Hello, @harry_choi
Thanks for your update.
From my understanding, it is correct for your address map. the address you mentioned would be 0x80000000.
BR
Chenyin
Hello Chenyin,
Per my understanding,
If M7_0 core writes the data '0x12345678' on DDR address 0x60000000, then which address has the data '0x12345678' on A53 core side?
Is below address map correct ?
M7_0 DDR address <--> A53 DDR address
-----------------------------------------------------
0x6000.0000 ~ 0x7FFF.FFFF <-> 0x8000.0000 ~ 0x9FFFF.FFFF
0x8000.0000 ~ 0x9FFF.FFFF <-> 0xA000.0000 ~ 0xBFFFF.FFFF
0xA000.0000 ~ 0xBFFF.FFFF <-> 0xC000.0000 ~ 0xDFFFF.FFFF
0xC000.0000 ~ 0xDFFF.FFFF <-> 0xE000.0000 ~ 0xFFFFF.FFFF
Thanks,
Harry
Hello, @harry_choi
Thanks for the reply.
Yes, if the DDR is initialized by the M7, then it do not need to re-initialized from A53 side.
BR
Chenyin
Hello Chenyin,
Thanks for your reply.
Your answer is valid even though there is no DDR initialization on A53 side, correct?
I will check on A53 core side why A53 BL cannot read or write correctly on 0xFF000000 address more.
BR,
Harry
Hello, @harry_choi
Thanks for your post.
From my understanding, from A53 view, it could be started from 0x80000000, not 0x60000000.
BR
Chenyin