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MPC5777C - How many planes does the C55FMC have?

Hello!

I know that the PFLASH has two AHB ports associated to it. Each port is connected to a mini-cache which prefetches data from the C55FMC embedded flash memory. So, even the caches being isolated, they are connected to the same memory array. So, when the L1 instruction cache tries to retrieve instructions from the flash, there might be inter-core timing interference associated to the shared flash.

I discovered that in a typical architechture of a flash there is a structure called "plane". A plane is a group of flash blocks that could be accessed in parallel. This raises me some questions:

1) How many planes does the C55FMC has?

2) If it has more than one plane, can I write data in specific flash planes? A possible scenario would be writing the instructions of each core in different planes to mitigate inter-core timing interference.

3) Can I force each mini-cache to prefetch data from different planes? A possible scenario would be each core reading instructions from specific mini-caches and each mini-cache prefetching data from different planes, mitigating inter-core timing interference.

Best regards,

Matheus.

Re: MPC5777C - How many planes does the C55FMC have?

I don’t know the term “plane” in this context.

If you mean parallel read access, there is no such defined and access time may be increase by mentioned mini cache (4 ways, 4 sets per 256 bit). How I said before, there are two flash ports.

Another point is that there may read-while-write what is kind of parallel access - you can execute code/read data from one flash partition while erasing/programming another partition.

If you mean some true dual port operation as it can be present with some RAMs (graphical for instance), there is no such feature there. So I would apparently answered that there is only one plane (using your terminology).