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[#1]

Is it possible to simulate LIN's slave machine by UART on this chip?

Hello, everyone

According to the MPC5748G chip manual, only LIN0 supports master-slave mode. I want to make all LIN support master-slave mode in a certain sense through simulation. Is it possible to simulate LIN's slave machine by UART on this chip?

I want to use UART to receive LIN's frame header to determine if I need to simulate the slave's reply function. But UART receives whole bytes, how to receive the 13-bit low level synchronization interval in the frame header? I have seen similar features in other chips (STM32) that can receive or send the 13-bit low level when enabled. Is there a similar function on our MPC5748G?

H-chips

MPC5748G-GW-RDB 

Re: Is it possible to simulate LIN's slave machine by UART on this chip?

Hi,

next byte is received normally. 

BR, Petr

Re: Is it possible to simulate LIN's slave machine by UART on this chip?Thank you for your answer. When UART receives break, does it read a byte and find that the format is not satisfied, and then it continues to receive the next byte immediately? Or discard the current message? I don't quite understand how to process the data byte-by-byte after receiving an error frame.Re: Is it possible to simulate LIN's slave machine by UART on this chip?

Hi,

 this will be hardly done using UART mode. There is no break detection/generation feature.
To emulate Slave you can get frame error when break is received, then process payload and checksum byte by byte.
But for sending break in master I see no option. Maybe changing word length, but this is only possible in Init mode.

BR, Petr