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[#1]

MPC5777C - Questions about XBAR behavior

Hello!

I have some questions about the XBAR:

1 - I saw in the MPC5777C reference manual that the crossbar switch "supports for burst transfers of up to 16 beats of data". What does the unit "beat" means?

2 - Does each slave port has an independent buffer to store the data to be bursted or the buffer is shared among slave ports?

3 - Does the crossbar switch reorder the accesses to be sent to the slave ports to optimize some latency? For example: Imagine a scenario in which core0 performs 4 contiguous read requests to the SRAM, then core1 performs 1 read request and then core0 performs other 3 read requests that are contiguous to the last 4 read requests. Does the SRAM receive these requests in this exact sequence or is there any possibility that the requests are reordered to reduce overrall access latency?

Best regards, 

Matheus

Re: MPC5777C - Questions about XBAR behavior

1) 'beat' means how many times data are transferred.

Normal read/write is single beat transfer - considering 32-bit transfer size, 4 bytes are transferred.

If you have 4-beat burst transfers per 32-bit, 16 bytes are transferred.

2) It is not about buffer but burst transfers are faster because shortened overhead. Although SRAM controller contains late write buffer, this have 64-bit and burst transaction are probably not affected by this. There is no other buffer there. And late write buffer is present only in the SRAM slave port.

3) These are isolated single beat transfers. Re-ordering would not lead in any time saving. Another topic is read/write burst in case cache line filling of draining, which could work same way as burst on EBI (27.5.2.5 Burst Transfer) i.e. wrap bursts when firstly read address is read first, then the rest.

Note that burst accesses are affected by setup in Platform Configuration Module (PCM).