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1845639_en-US

1845639_en-US

The IVOR1 IRQ is caused by SPC5746R triggering an interrupt.

I am currently using the SPC5746RMMT5 chip and enter the IVOR1_IRQ interrupt when debugging eTPU set2 with S32 DS for Power.
The TG function is working fine for now, but when I set the Crank capture interrupt, it triggers the IVOR1_IRQ interrupt.
Check that the MCSR is not incorrectly set.

JiandongDing_0-1712887009832.png

How can I fix it?

Re: The IVOR1 IRQ is caused by SPC5746R triggering an interrupt.

Thank you very much. You have solved this problem for me!

Re: The IVOR1 IRQ is caused by SPC5746R triggering an interrupt.

If you are using original etpu sets with MPC57xx devices, it is possible it is needed to initilize ECC as follows:

#define eTPU_AB_SPRAM_start 0xFFCC8000
#define eTPU_AB_SPRAM_end 0xFFCCBFFF

/* Clear all ETPU SRAM memories due to ECC */
// eTPU A/B parametric RAM
for (i=eTPU_AB_SPRAM_start; i{
(*(uint32_t *) i) = 0;
}

In the past I made example code for this:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5746R-eTPU-original-set1-integration-...


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Last update:
‎11-21-2025 04:15 PM
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