Hello,
I used flexcan's RxFIFO for CAN development.
How can I detect dominant time-out through flexcan or other methods.
What interrupts or interfaces does flexcan have?
Dominant time-out refers to the detection of the SOF segment of the CAN frame as shown in the figure
Hi,
1) No, just IDLE, TX and RX bits of ESR1 shows that something is on the bus.
2) there is no indication for a message that is not matched in neither MB nor RXFIFO, frame is lost.
BR, Petr
Sorry, there was an error in my description. Let me rephrase the problem.
1.Can flexcan notify me through interrupts or other means when it changes from an recessive state to an dominant state on the CAN bus.
2.Can flexcan notify me through interrupts or other means when receiving frames outside of the filter.
Hi,
why would dominant time-out refer to the detection of the SOF segment? SOF is single dominant bit and is normally detected by module. Long time dominant condition will be detected via stuff or form errors and error interrupt will be called if enabled. Module tolerates 5 consecutive dominant bits then stuff bit (opposite level) must be detected.
Dominant time out feature is obviously implemented on CAN transceiver to disable transmitter when TXD line is held low for extended/defined time, so a node will not disturb bus anymore.
BR, Petr