MCG configuration in mqx for k65f180m for using internal reference clock

[annamol]

Hi,

I am trying to configure the internal reference clock for K65F180m in mqx. I have read the utasker documentation on MCG modes and have gone through the reference manual. I have certain doubts regarding MCG. It would be of great help if anyone can clarify them

• For using the IRC, I could find only these configurations. Is there anything more missing (the values configured in registers are mentioned in barckets)
  • MCG_C1-> CLKS(1) ,IREFS (1), IRCLKEN(1)
  • MCG_C7 ->OSCSEL(2)
  • OSC_CR ->ERCLKEN (0)
  • MCG_S ->IREFST(1),CLKST(1),IRCST(1)
  • SIM_SOPT2 ->PLLFLLSEL (3), SIM_SOPT2_USBSRC_MASK

  • SIM_SCGC4 ->SIM_SCGC4_USBOTG_MASK;

  • USB0_CLK_RECOVER_IRC_EN ->USB_CLK_RECOVER_IRC_EN_REG_EN_MASK
  •   USB0_CLK_RECOVER_CTRL  ->USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK
• When i add the above configurations in my project, the debugging session stops. It might be because of the mismatch in clock. But I read in a post that Jlink OpenSDA won't have issue with lower clock. but mine is openSDA.
• In mqx project, i made the following changes in bsp_cm.c file. i am not sure if this is correct or not
  • for making that change i commented off the OSC_CR and mode changing sections in pe_initialize_hardware

void __pe_initialize_hardware(void)

{

    /* OSC Configure */

    OSC_CR |= ~OSC_CR_ERCLKEN_MASK;

//    /* after enter FEI Mode */

//    Cpu_SetMCGModeFBE(0);

//    Cpu_SetMCGModePBE(0);

//    Cpu_SetMCGModePEE(0);

}

• Is it possible to completely remove the external crystal and power up the board. In all the initialization sections, I could see the external reference clock being used in code. Can we do it using the 32KHz and 4MHz crystals available?
• Can we generate the code to use internal reference clock alone for the K65  MCU using processor expert? Is there any document available for the same
• In the MCG documentation, we  have MCG in FEI mode when it comes out of reset, Is this reset referring to a full system reset? Does this mean that an external crystal is needed for the MCU operation. Is crystal less operation possible, any document available for the same.

[mjbcswitzerland]

Hi

You have not specified clearly which internal reference clock that you would like to use - from the code I assume that it is IRC48M since this is enabled; IRC48MHz can be used as direct core clock source or as reference for PLL or FLL.

After a reset (any type) the MCG starts in FEI mode, meaning that the 32kHz IRC is being used as source for the FLL and the core is clocked at around 21MHz.

You can initialise and operate without any external oscillator.

The only time that an external crystal/oscillator is needed for the K65 is when you need to use HS USB PHY, in which case a 12MHz, 16MHz or 24MHz crystal/oscillator is required for its PLL to reference to.

Regards

Mark

P.S.

This is a strange command - it is setting all bits apart from the OSC_CR_ERCLKEN_MASK:

OSC_CR |= ~OSC_CR_ERCLKEN_MASK;

[annamol]

Hi,

When i make changes in the bsp for using the internal clock, the code doesn't get executed. It stays in the mcg loop forever waiting for lockup. I tried generating a code for K53 using processor expert (K65 is not supported in PEx 10.4) disabling the system oscillator. I enabled the mcg mode as BLPI and used the 4MHz clock. Then the generated code was imported to a new IAR C project. But there also same issue.

Anyone having the configuration needed to startup using internal oscillator. 4MHz fast IRC is also ok. The 48MHz IRC is internal to the micro controller right? Am i wrong?

[mjbcswitzerland]

Hi

It is still not clear which internal clock you want, but I am still assuming it is IRC48M, which is internal to the processor.

The following code switches the core to work directly with this clock.

    MCG_C7 = MCG_C7_OSCSEL_IRC48MCLK;                                    // route the IRC48M clock to the external reference clock input (this enables IRC48M)
    SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLEX_CLOCK_DIVIDE - 1) << 20) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides
    MCG_C1 = (MCG_C1_IREFS | MCG_C1_CLKS_EXTERN_CLK);                    // switch IRC48M reference to MCGOUTCLK
    while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {}      // wait until the new source is valid (move to FBI using IRC48M external source is complete)
    MCG_C2 |= MCG_C2_LP;                                                 // set bypass to disable FLL and complete move to BLPE (in which PLL is also always disabled)

Regards

Mark