Bug Report: Cortex-A5 PSP boot.S interrupt stack.

[billpringlemeir]

I think that we need to use 'R0' and not 'R1' as it is not set anywhere.  It probably doesn't matter much as interrupts should be disabled until the actual interrupt stack is setup latter.  This is line 143 of MQX4.0.2 and 139 of MQX-4.1 in boot.S.  Is this where I should report issues or is there some SPR system?  Am I allowed to show the code lines or does this violate the MQX license?

[alejandrolozan1]

Hi Bill,

You can share the correction here, there is no issue or problem about it.

Best Regards,

Alejandro

[billpringlemeir · Accepted solution]

diff --git a/mqx/source/psp/cortex_a/core/A5/boot.S b/mqx/source/psp/cortex_a/core/A5/boot.S
index 7ae8de3..f2b33f1 100644
--- a/mqx/source/psp/cortex_a/core/A5/boot.S
+++ b/mqx/source/psp/cortex_a/core/A5/boot.S
@@ -131,12 +131,12 @@ ASM_LABEL(reset)
 
                 /* set fast interrupt (FIQ) mode stack */
                 msr cpsr_c, #PSP_PSR_MODE_FIQ | PSP_PSR_CTRL_DIS_FIQ | PSP_PSR_CTRL_DIS_IRQ
                 ldr sp, =FIQ_STACK_ADDR
 
                 /* set interrupt (IRQ) mode stack */
                 msr cpsr_c, #PSP_PSR_MODE_IRQ | PSP_PSR_CTRL_DIS_FIQ | PSP_PSR_CTRL_DIS_IRQ
                 ldr r0, =__BOOT_STACK_ADDRESS
-                mov sp, r1
+                mov sp, r0
 
                 /* set abort mode stack */
                 msr cpsr_c, #PSP_PSR_MODE_ABORT | PSP_PSR_CTRL_DIS_FIQ | PSP_PSR_CTRL_DIS_IRQ
                 msr cpsr_c, #PSP_PSR_MODE_ABORT | PSP_PSR_CTRL_DIS_FIQ | PSP_PSR_CTRL_DIS_IRQ

Later, the value 'r1' is updated, but at this point in the code, the value is random from reset.  There is also some commented code before that was attempting to set 'r1', but it is not active in MQX-4.1.

[alejandrolozan1]

Thanks a lot Bill!!

Best Regards,

Alejandro