what is Minimum Alignment Requirement for MPC5674F Interrupt Vector Table Section in Linker script ?

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what is Minimum Alignment Requirement for MPC5674F Interrupt Vector Table Section in Linker script ?

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CNarendra
Contributor III

Hi,

I am trying to understand the correct alignment for the interrupt vector table in linker scripts for MPC5674F.

  • The documentation mentions "vector offset must be located on a quad-word (16-byte) aligned location".

  • The SDK uses ALIGN(0x1000), but I observed that ALIGN(0x100) also works, while ALIGN(0x10)—which is still 16-byte aligned—does not work.

  • Why does ALIGN(0x10) fail, even though it is technically 16-byte aligned?

  • Is there any hardware or software reason I should prefer ALIGN(0x100) or 0x1000 over 0x10?

Appreciate any clarification on why higher alignment is required beyond the stated 16-byte boundary. it would be helpful if we get these details present in any manual.

CNarendra_0-1761806175133.png

CNarendra_1-1761806203306.png


Thanks 
Narendra.C

@davidtosenovjan ,@PetrS

MPC5674F 

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Theoretically 0x10 could be enough, but if you have the whole vector table in one aligned block i.e. 16 IVORs per 16 bytes, it needs to be aligned to 256 (0x100).

I am not sure what SDK uses, I would recommend to keep it at highest value. It may be due to compatibility with other devices where IVOR addresses are fixed, thus there is requirement for exact alignment, it may be also due to MMU or MPU setup or similar.

I believe your own baremetal code would work with 0x10 alignment.

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CNarendra
Contributor III

Hi @davidtosenovjan 

I’m trying to understand where IVOR16–IVOR63 (reserved / implementation-dependent) should be placed in the linker script for MPC5674F.
Book_EUMBook_EUM

MAP FileMAP File

from SDK generated files there are no vector defined for IVOR16-63 properly. 

The e200z7 core reference manual lists IVOR0–15 as defined and IVOR16–63 as reserved or implementation-dependent. Should we still allocate space for IVOR16–63 in the vector table section?

Also, I noticed that ALIGN(0x10) (16-byte alignment) is not working at all with RTOS Application and MMU enabled.

Thanks & Regards 
Narendra.C

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davidtosenovjan
NXP TechSupport
NXP TechSupport

There are defined vectors 32-35 foe SPE/EFPU, so if application uses these engines, it should be define otherwise it is not necessary in principle.

davidtosenovjan_1-1762190519514.png

RTOS may have specific requirement that is needed to keep.

 

 

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