void SysClk_Init(void)
{
MC_CGM.AC3_SC.B.SELCTL = 0x01; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01; //connect XOSC to the PLL1 input
// Set PLL0 to 400 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x40021014; // PREDIV = 1, MFD = 20, RFDPHI = 2, RFDPHI1 = 8
MC_ME.RUN_MC[0].R = 0x00130070; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
// Set PLL1 to 600 MHz with 40MHz XOSC reference
PLLDIG.PLL1DV.R = 0x0001001E; // MFD = 30, RFDPHI = 1
MC_ME.RUN_PC[0].R = 0x000000FE; // enable peripherals run in all modes
MC_ME.RUN_PC[1].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[2].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[3].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[4].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[5].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[6].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_PC[7].R=0x000000FE; /* Peripheral ON in every mode */
MC_ME.RUN_MC[0].R = 0x001300F4; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL1
MC_CGM.SC_DIV_RC.R = 0x00000001; //! System clock divider ratios will change with next update. Not required for Cut 1.
MC_CGM.DIV_UPD_TYPE.R = 0x80000000; //! System clock divider ratios updated on writing MC_CGM.DIV_UPD_TRIG. Not required for Cut 1.
MC_CGM.SC_DC2.R = 0x800B0000; // PBRIDGEA/PBRIDGEB_CLK at syst clk div by 12 ... (50 MHz)
MC_CGM.SC_DC1.R = 0x80050000; // SXBAR_CLK at syst clk div by 6 ... (100 MHz)
MC_CGM.SC_DC0.R = 0x80020000; // FXBAR_CLK, BD_CLK, IOP_CLK at syst clk div by 3 ... (200 MHz)
MC_CGM.SC_DC3.R = 0x80010000; // COMP/CHKR_CLK at syst clk div by 2 ... (300 MHz)
MC_CGM.SC_DC4.R = 0x800A0000; // CLKOUT at syst clk div by 11 ... (54.55 MHz)
MC_CGM.DIV_UPD_TRIG.R = 0xfeedface; //! System clock divider ratio updates triggered. Not required for Cut 1.
while (MC_CGM.DIV_UPD_STAT.B.SYS_UPD_STAT == 1) //! Wait for System Clock Divider Update Status == 0. Not required for Cut 1.
{
}
MC_ME.PCTL3.R = 0;
MC_ME.PCTL15.R = 0;
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
MC_CGM.AC0_SC.R = 0x02000000; // Select PLL0 for auxiliary clock 0
MC_CGM.AC0_DC0.R = 0x80070000; // PER_CLK : Enable aux clk 0 div by 8 (50 MHz)
MC_CGM.AC0_DC3.R = 0x80030000; // DSPI_CLK4/5/6 : Enable aux clk 0 div by 4 (100 MHz)
MC_CGM.AC0_DC4.R = 0x80030000; // DSPI_CLK1, LIN_CLK : Enable aux clk 0 div by 4 (100 MHz)
//MC_CGM.AC2_SC.R = 0x02000000; // Select PLL0 for auxiliary clock 2
MC_CGM.AC2_DC0.R = 0x80090000; // FLEXRAY_CLK : Enable aux clk 2 div by 10 (40 MHz)
MC_CGM.AC10_DC0.R=0x800F0000; /*! program Aux Clock 10 divider 0 (ENET) -> Divide by 15 + 1. 400MHz / 16 = 25MHz | MC_CGM.AC10_DC0 */
MC_CGM.AC7_SC.R=0x02000000; /*PLL0*/
MC_CGM.AC7_DC0.R = 0x800F0000; /*400MHz/16 = 25MHz use sysclk1 op to PHY*/
MC_CGM.AC8_SC.R = 0x01000000; // Select XOSC for auxiliary clock 8
MC_CGM.AC8_DC0.R = 0x80000000; // CAN_CLK : Enable aux clk 8 div by 1 (40 MHz)
}
extern void xcptn_xmpl(void);
void ebi_config(){
EBI.MCR.R = 0x00000000;
// Configure Control pins // Port Pin Number MSCR_SSS Func. Module Description Dir BGA416 BGA512
SIUL2.MSCR_IO[289].R = 0x12380003; // PV[0] 289 0000_0011 CLKOUT EBI EBI Clock Output O AA26 AG30
SIUL2.MSCR_IO[290].R = 0x12380003; // PV[1] 290 0000_0011 /OE EBI EBI Output Enable Signal O AA24 AF30
SIUL2.MSCR_IO[291].R = 0x12380003; // PV[2] 291 0000_0011 RD_WR EBI EBI Read_Write Enable Output O AA23 AF29
SIUL2.MSCR_IO[292].R = 0x12380003; // PV[3] 292 0000_0011 /CS2 EBI EBI Chip Select 2 Output O Y24 AE30
SIUL2.MSCR_IO[293].R = 0x12380003; // PV[4] 293 0000_0011 /CS1 EBI EBI Chip Select 1 Output O Y25 AE29
SIUL2.MSCR_IO[294].R = 0x12380003; // PV[5] 294 0000_0011 /CS0 EBI EBI Chip Select 0 Output O Y26 AD30
SIUL2.MSCR_IO[296].R = 0x12380003; // PV[7] 296 0000_0011 /TS EBI EBI Transfer Start Output O W24 AD29
// Configure Data pins // Port Pin Number MSCR_SSS Func. Module Description Dir BGA416 BGA512
SIUL2.MSCR_IO[257].R = 0x12380003; // PS[0] 257 0000_0011 D30 EBI EBI Data[30] Signal I/O AD18 AJ12
SIUL2.MSCR_IO[258].R = 0x12380003; // PS[1] 258 0000_0011 D29 EBI EBI Data[29] Signal I/O AE18 AK12
SIUL2.MSCR_IO[259].R = 0x12380003; // PS[2] 259 0000_0011 D28 EBI EBI Data[28] Signal I/O AF18 AJ13
SIUL2.MSCR_IO[260].R = 0x12380003; // PS[3] 260 0000_0011 D26 EBI EBI Data[26] Signal I/O AD19 AK13
SIUL2.MSCR_IO[261].R = 0x12380003; // PS[4] 261 0000_0011 D24 EBI EBI Data[24] Signal I/O AE19 AJ14
SIUL2.MSCR_IO[262].R = 0x12380003; // PS[5] 262 0000_0011 D23 EBI EBI Data[23] Signal I/O AF19 AK14
SIUL2.MSCR_IO[263].R = 0x12380003; // PS[6] 263 0000_0011 D20 EBI EBI Data[20] Signal I/O AD20 AJ15
SIUL2.MSCR_IO[264].R = 0x12380003; // PS[7] 264 0000_0011 D16 EBI EBI Data[16] Signal I/O AE20 AK15
SIUL2.MSCR_IO[265].R = 0x12380003; // PS[8] 265 0000_0011 D31 EBI EBI Data[31] Signal (LSB) I/O AF20 AJ16
SIUL2.MSCR_IO[266].R = 0x12380003; // PS[9] 266 0000_0011 D27 EBI EBI Data[27] Signal I/O AD21 AK16
SIUL2.MSCR_IO[267].R = 0x12380003; // PS[10] 267 0000_0011 D21 EBI EBI Data[21] Signal I/O AE21 AJ17
SIUL2.MSCR_IO[268].R = 0x12380003; // PS[11] 268 0000_0011 D25 EBI EBI Data[25] Signal I/O AF21 AK17
SIUL2.MSCR_IO[269].R = 0x12380003; // PS[12] 269 0000_0011 D19 EBI EBI Data[19] Signal I/O AD22 AJ18
SIUL2.MSCR_IO[270].R = 0x12380003; // PS[13] 270 0000_0011 D22 EBI EBI Data[22] Signal I/O AE22 AK18
SIUL2.MSCR_IO[271].R = 0x12380003; // PS[14] 271 0000_0011 D18 EBI EBI Data[18] Signal I/O AD23 AJ19
SIUL2.MSCR_IO[272].R = 0x12380003; // PS[15] 272 0000_0011 D17 EBI EBI Data[17] Signal I/O AE23 AK19
SIUL2.MSCR_IO[273].R = 0x12380003; // PT[0] 273 0000_0011 D14 EBI EBI Data[14] Signal I/O AF22 AJ21
SIUL2.MSCR_IO[274].R = 0x12380003; // PT[1] 274 0000_0011 D11 EBI EBI Data[11] Signal I/O AF23 AK21
SIUL2.MSCR_IO[275].R = 0x12380003; // PT[2] 275 0000_0011 D12 EBI EBI Data[12] Signal I/O AB24 AJ22
SIUL2.MSCR_IO[276].R = 0x12380003; // PT[3] 276 0000_0011 D15 EBI EBI Data[15] Signal I/O AC24 AK22
SIUL2.MSCR_IO[277].R = 0x12380003; // PT[4] 277 0000_0011 D8 EBI EBI Data[8] Signal I/O AD24 AJ23
SIUL2.MSCR_IO[278].R = 0x12380003; // PT[5] 278 0000_0011 D13 EBI EBI Data[13] Signal I/O AE24 AK23
SIUL2.MSCR_IO[279].R = 0x12380003; // PT[6] 279 0000_0011 D4 EBI EBI Data[4] Signal I/O AF24 AJ24
SIUL2.MSCR_IO[280].R = 0x12380003; // PT[7] 280 0000_0011 D7 EBI EBI Data[7] Signal I/O AB25 AK24
SIUL2.MSCR_IO[281].R = 0x12380003; // PT[8] 281 0000_0011 D3 EBI EBI Data[3] Signal I/O AC25 AJ25
SIUL2.MSCR_IO[282].R = 0x12380003; // PT[9] 282 0000_0011 D0 EBI EBI Data[0] Signal (MSB) I/O AD25 AK25
SIUL2.MSCR_IO[283].R = 0x12380003; // PT[10] 283 0000_0011 D5 EBI EBI Data[5] Signal I/O AE25 AJ26
SIUL2.MSCR_IO[284].R = 0x12380003; // PT[11] 284 0000_0011 D10 EBI EBI Data[10] Signal I/O AF25 AK26
SIUL2.MSCR_IO[285].R = 0x12380003; // PT[12] 285 0000_0011 D9 EBI EBI Data[9] Signal I/O AB26 AJ27
SIUL2.MSCR_IO[286].R = 0x12380003; // PT[13] 286 0000_0011 D2 EBI EBI Data[2] Signal I/O AC26 AK27
SIUL2.MSCR_IO[287].R = 0x12380003; // PT[14] 287 0000_0011 D1 EBI EBI Data[1] Signal I/O AD26 AJ28
SIUL2.MSCR_IO[288].R = 0x12380003; // PT[15] 288 0000_0011 D6 EBI EBI Data[6] Signal I/O AE26 AK28
// Configure Address pins // Port Pin Number MSCR_SSS Func. Module Description Dir BGA416 BGA512
SIUL2.MSCR_IO[299].R = 0x12380003; // PV[10] 299 0000_0011 A10_WE2 EBI EBI Address 10 (MSB) O V24 AB29 (Write_Byte Enable 2 Output Signal)
SIUL2.MSCR_IO[300].R = 0x12380003; // PV[11] 300 0000_0011 A11_WE3 EBI EBI Address 11 O V25 AB30 (Write_Byte Enable 3 Output Signal)
SIUL2.MSCR_IO[301].R = 0x12380003; // PV[12] 301 0000_0011 A12 EBI EBI Address 12 Output Signal O V26 AA29
SIUL2.MSCR_IO[302].R = 0x12380003; // PV[13] 302 0000_0011 A14 EBI EBI Address 14 Output Signal O U24 AA30
SIUL2.MSCR_IO[303].R = 0x12380003; // PV[14] 303 0000_0011 A13 EBI EBI Address 13 Output Signal O U25 Y29
SIUL2.MSCR_IO[304].R = 0x12380003; // PV[15] 304 0000_0011 A15 EBI EBI Address 15 Output Signal O U26 Y30
SIUL2.MSCR_IO[305].R = 0x12380003; // PW[0] 305 0000_0011 A20 EBI EBI Address 20 Output Signal O U23 U29
SIUL2.MSCR_IO[306].R = 0x12380003; // PW[1] 306 0000_0011 A16 EBI EBI Address 16 Output Signal O T24 U30
SIUL2.MSCR_IO[307].R = 0x12380003; // PW[2] 307 0000_0011 A17 EBI EBI Address 17 Output Signal O T25 T29
SIUL2.MSCR_IO[308].R = 0x12380003; // PW[3] 308 0000_0011 A18 EBI EBI Address 18 Output Signal O T26 T30
SIUL2.MSCR_IO[309].R = 0x12380003; // PW[4] 309 0000_0011 A22 EBI EBI Address 22 Output Signal O R24 R29
SIUL2.MSCR_IO[310].R = 0x12380003; // PW[5] 310 0000_0011 A19 EBI EBI Address 19 Output Signal O R25 R30
SIUL2.MSCR_IO[311].R = 0x12380003; // PW[6] 311 0000_0011 A26 EBI EBI Address 26 Output Signal O R26 P29
SIUL2.MSCR_IO[312].R = 0x12380003; // PW[7] 312 0000_0011 A23 EBI EBI Address 23 Output Signal O P24 P30
SIUL2.MSCR_IO[313].R = 0x12380003; // PW[8] 313 0000_0011 A21 EBI EBI Address 21 Output Signal O P25 N29
SIUL2.MSCR_IO[314].R = 0x12380003; // PW[9] 314 0000_0011 A25 EBI EBI Address 25 Output Signal O P26 N30
SIUL2.MSCR_IO[315].R = 0x12380003; // PW[10] 315 0000_0011 A27 EBI EBI Address 27 Output Signal O N23 M29
SIUL2.MSCR_IO[316].R = 0x12380003; // PW[11] 316 0000_0011 A28 EBI EBI Address 28 Output Signal O N24 M30
SIUL2.MSCR_IO[317].R = 0x12380003; // PW[12] 317 0000_0011 A30 EBI EBI Address 30 Output Signal O N25 L29
SIUL2.MSCR_IO[318].R = 0x12380003; // PW[13] 318 0000_0011 A29 EBI EBI Address 29 Output Signal O N26 L30
SIUL2.MSCR_IO[319].R = 0x12380003; // PW[14] 319 0000_0011 A31 EBI EBI Address 31 (LSB) Output O M24 K29
SIUL2.MSCR_IO[320].R = 0x12380003; // PW[15] 320 0000_0011 A24 EBI EBI Address 24 Output Signal O M25 K30
}
extern uint32_t EXTERNAL_FLASH_ADDR[];
void ebi_detect(uint32_t cs_num){
volatile uint32_t result=0x0;
//*(uint32_t*)ebi_struct[cs_num].brx=0x2000100B;
EBI.BR0.R = 0x2000000B;
EBI.OR0.R = 0xff000000;
// Check Manufacturer ID:
// EXTERNAL_FLASH_ADDR[0x1554] = 0xAA;
// EXTERNAL_FLASH_ADDR[0xAA8] = 0x55;
asm("e_nop");
result=*(uint32_t *)(0x200FFFFF); // 4. Store data located at "0x20000004" - read address BA + X01
*(uint32_t *)(0x20001554)=0xAA; // 1. Unlock Cycle
asm("e_nop");
*(uint32_t *)(0x20000AA8)=0x555; // 2. Unlock Cycle
asm("e_nop");
*(uint32_t *)(0x20001554)=0x90909090; // 3. Cycle Program Command
result=*(uint32_t *)(0x20000000); // 4. Store data located at "0x20000000" - read address BA + X00
// Check Device ID:
*(uint32_t *)(0x20001554)=0xAAAAAAAA; // 1. Unlock Cycle
*(uint32_t *)(0x20000AA8)=0x55555555; // 2. Unlock Cycle
*(uint32_t *)(0x20001554)=0x90909090; // 3. Unlock Cycle
result=*(uint32_t *)(0x20000004); // 4. Store data located at "0x20000004" - read address BA + X01
result=*(uint32_t *)(0x20000038); // 5. Store data located at "0x20000038" - read address BA + X0E
result=*(uint32_t *)(0x2000003C); // 6. Store data located at "0x2000003C" - read address BA + X0F
// *(uint32_t*)ebi_struct[cs_num].brx=0x2000100A; //
EBI.BR0.R = 0x2000100A ;//- Clear Valid bit
}
