We are using the MPC5566 and interfacing with a FPGA. The FPGA access is not deterministic, on some IP's within the FPGA the access takes longer. To avoid the longest access time by setting waitstates we want to use the TA functionality only available with a non chipselect access. How can this configured?
Hi, on this legacy device there is only one option how to achieve this and it is non-CS access. Please pay attention to my bulletin below, section 1: