Hello,
PBRIDGE_0_CLK is derived from System Clock which is 264MHz (PLL0).

PBRIDGE_0_CLK is set by MC_CGM_SC_DC_3 register. DIV bits in this register are set to 3 by default, so divider is 4. This tells you that PBRIDGE clock is 66MHz (PLL0/4 ....264/4=66)
Please ignore SC_CGM_AC13 register settings. This is not related to PBRIDGE clock settings.
2) In general, this bridge allows masters to access (write and read) the slaves. So, if DMA (master) wants to access to UART (slave), this must be enabled in AIPS bridge. Please read chapter 22 in MPC5775K reference manual.
3) It could be little bit complicated. At first, check if you have correctly configured pins and if the the pins you configured are routed to UART transceiver. Second, try to send characters without DMA and check, if it works. If yes, check DMA settings. If no, there will be most probably some issue with pad settings.
Regards,
Martin