config switch PLLCFG0 PLLCFG1 RSTCFG WKPCFG BOOTCFG0 BOOTCFG1 TEST EVTI 怎么控制

[smallyang]

您好,  我有个新的问题。   我想问下电路板这些引脚怎么设置才能用调试器从jtag口下载调试呢?

Hello, I have a new question. I would like to ask how to set these pins of the circuit board to download debugging from the jtag port with the debugger?

[davidtosenovjan · Accepted solution]

If you have
CONFIG enable = OFF, i.e. rest is ignored and default, internal, crystal reference is used

equivalent configuration is
CONFIG enable = ON, i.e. RSTCFG = config from pins below
BOOTCFG1=OFF,
BOOTCFG2=OFF, i.e. internal
PLLCFG0=ON,
PLLCFG1=OFF and i.e. crystal reference
WKPCFG = ON,

BOOTCFG/PLLCFG description you may find in the device's RM.

Anyway PLLCFG configuration needs to fit used HW setup, BOOTCFG should not matter in the context of debugger connection and downloading SW unless device is censored.

[smallyang]

还有 EVTI#需要怎么配置呢

And how to configure EVTI#

[smallyang]

好的非常感谢您的回答，请问我们这个硬件需要怎么配pll呢？

Ok, thank you very much for your answer. May I ask how we need pll for this hardware?