MPC5775E-EVB

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MPC5775E-EVB

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AndrewZhu
Contributor II

Hello,

I am developing a qt based GUI app for MPC5775E 3-phase PMSM Development Kit link . I have implemented the UART communication using eSCI module on the board.

Spoiler
void eSCI_ISR (void){
if (eSCI_A.IFSR1.B.RDRF)
{
if (RXindex < sizeof(bufferIn)) {
bufferIn[RXindex] = eSCI_A.SDR.B.RDTD;
RXindex++;
 
}
if (RXindex >= sizeof(bufferIn)) {
RXindex = 0;
memcpy(&data_in, bufferIn, sizeof(DataUART));
}
 
eSCI_A.IFSR1.R = eSCI_IFSR1_RDRF_MASK;
}
 
    if (eSCI_A.IFSR1.B.TDRE && (eSCI_A.IFSR1.B.TC || UARTbusy)) // Check both TDRE and TC flags
    {
    UARTbusy = FALSE;
        if (startByteSent == FALSE){
            eSCI_A.SDR.B.RDTD = 0x02; //start byte
            startByteSent = TRUE;
        } else if (TXindex < sizeof(bufferOut))
        {
            eSCI_A.SDR.B.RDTD = bufferOut[TXindex];
            TXindex++;
        } else if(stopByteSent == FALSE) {
            eSCI_A.SDR.B.RDTD = 0x03; //stop byte
            stopByteSent = TRUE;
        }
 
        if(stopByteSent == TRUE && eSCI_A.IFSR1.B.TC){ // Check TC flag again before concluding transmission
            TXindex = 0;
            counter++;
            startByteSent = FALSE;
            stopByteSent = FALSE;
            eSCI_A.CR1.B.TIE = 0; // Disable transmit interrupt
        }
 
//        eSCI_A.IFSR1.R = eSCI_IFSR1_TDRE_MASK | eSCI_IFSR1_TC_MASK; // Clear TDRE and TC flags
        eSCI_A.IFSR1.B.TDRE = 1;
        eSCI_A.IFSR1.B.TC = 1;
    }
}

 

Basically I have 2 buffers: one for reading and the other one for writing to serial. Function I attached in spoiler is interrupt service routine for eSCI module. My idea is to turn on interrupt from TDRE flag when I want to send the contents of bufferOut. It will send a byte at a time and then TDRE interrupt will happen which would send next byte of a buffer. When the whole buffer and stopByte were sent, it turns off interrupt from TDRE. This code works, but after around 200 - 300 successful transmissions (counted by a "counter" variable) eSCI stops setting the TDRE flag at all. What is more interesting is that RDRF flag works as usual so I can send signals from PC and recieve them.
I tried checking every single register related to eSCI, running only 1 core, removing buffer and instead just sending 0x05, but it did not help. This forum is my last resort, because I do not see any potential cause to this.
Thank you in advance and if more details are needed feel free to ask
Best regards

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1 Solution
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AndrewZhu
Contributor II

Sorry for late reply, I have found the solution for my problem. My issues with SCI were caused by my incorrect handling of Timer interrupt service routine. I did not stop the timer while servicing its interrupt and it seems it was somehow messing with sci interrupt. Maybe nesting idk.
Anyway thanks for your reply

View solution in original post

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AndrewZhu
Contributor II

Sorry for late reply, I have found the solution for my problem. My issues with SCI were caused by my incorrect handling of Timer interrupt service routine. I did not stop the timer while servicing its interrupt and it seems it was somehow messing with sci interrupt. Maybe nesting idk.
Anyway thanks for your reply

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AndrewZhu
Contributor II

I replaced 

        eSCI_A.IFSR1.B.TDRE = 1;
        eSCI_A.IFSR1.B.TC = 1;
With 
#define eSCI_IFSR1_RDRF_MASK 0x2000u
#define eSCI_IFSR1_TDRE_MASK 0x8000u
#define eSCI_IFSR1_TC_MASK 0x4000u

eSCI_A.IFSR1.R = eSCI_IFSR1_TDRE_MASK | eSCI_IFSR1_TC_MASK;

I tested it, but the issue still seems to be there. I also found out that it is not consistent on how many times the message is sent correctly. One time counter goes up to 397, but the next time it goes only up to 27 before the TDRE stops being triggered. 
Could this be caused by OpenSDA debugger? I am using the same USB port for both debugging and comms. I've read that OpenSDA allows for serial usage while debuging, but I am not sure.
I have attached the main.c to the comment.

V jakémkoliv případě děkuji za rychlou odpověď
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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @AndrewZhu 

in general, the idea is correct. What I see at first glance - you are using "bit access" to clear the flags. Please take a look at:

https://www.nxp.com/docs/en/engineering-bulletin/EB758.pdf

section "3.2 Status bit clearing".

Isn't this the root cause?

Regards,

Lukas

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