The ENET1 module does not function unless the Peripheral control register (MC_ME_PCTL6) is enabled

[H-chips]

工程文件：lwip_mpc5748g

开发板型号：2018 NXP B.V. MPC5748G-GW

按照 MPC5748G-GW-RDB_ExampleCodes-UserGuide中的步骤来进行ENET1的开发

但是当前连PING也不通过，通过论坛里的一些相关回答，尝试了在PC上增加ARP表，但是仍然PING不通，此时在翻阅文档时发现有标注错误问题，但是通过查看寄存器说明，不是很理解这里说的enable是指做出什么样的设置。

MPC5748G-GW-RDB 

[PetrS · Accepted solution]

Hi,

it is done in MC_ME which allows peripheral clock gating control based on the ME_RUN_PC0…7, ME_LP_PC0…7,
and ME_PCTLn registers. So the errata say you need to enable clock for MLB0 module too, so contig one of ME_RUN_PC0…7 and ME_PCTL6 and do Mode Transition. Refer to chapter Mode Entry Module (MC_ME) of the device RM for more info.
If using SDK in your project it should be enough to enable MLB0 clock within clock component and regenerate PE code. CLOCK_SYS_Init and CLOCK_SYS_UpdateConfiguration called in code should set MC_ME registers accordingly.
In debugger you can check MC_ME_PS0 to know MLB0 clock is active.

BR, Petr