Special Purpose Register Address

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Special Purpose Register Address

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aksharap97
Contributor I

Hello Support Team,

I also faced the issue which was described in one of the tickets raised few years back "MPC5602D Data flash issue".

https://community.nxp.com/thread/436288 

It was regarding flash corruption. Once the flash is corrupted, I see '???????' in the debugger and it ends in infinite reset loops. 

@Lukas Zadrapa : Reading through post, I got to know that, flash blocks needs to erased again. 

I went through the pdf and software code which was attached by you. And I managed to understand bit.

Do you have this alogorithm implemented in C code?

One more question,if I want to implement this in C code, how can i get the address of special purpose registers like MCSRR0, MSR, MCSR etc.

I also went through the e200z759CRM pdf (i.e Core Reference Manual), but somehow I could not figure out the base address of those registers. Could you please help me out in this ? I also went through VLEPEM pdf also.

What does 'lis' 'stw' 'lwz' instruction meant by?

What does @h @l meant by?

asm (lis r30, (address)@h);              \

asm (ori r30, r30, (address)@l);         \

asm (lwz r31, 0x0(r30));    

Thanks And Regards,

Akshara Prasad

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi,

@h chooses high 16-bit from specified value

@l chooses low 16-bit from specified value

these two lines just loads the address into r30 register, but it must be done in 2 steps because of limitation of instruction set

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi,

@h chooses high 16-bit from specified value

@l chooses low 16-bit from specified value

these two lines just loads the address into r30 register, but it must be done in 2 steps because of limitation of instruction set

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1,174 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

It is defined in core reference manual:

https://www.nxp.com/docs/en/reference-manual/e200z4RM.pdf 

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MSR register does not have SPR number, it is being accessed by special instruction mtmsr/mfmsr.

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