Hi,
I will summarize the answer to one post:
The Example will be hang at PLL stabilization in Sysclk_Init() on my EVB.
Could you please check, if you use 40MHz crystal? If no, you have to change PLL settings. I see I have incorrect comments in my code. Below is code with correct comments. I tested this code with 40MHz crystal and it works correct.
#define RUN0_MODE 0x4
static void Sysclk_Init(void)
{
CGM.AC3_SC.B.SELCTL =0x01; //connect (40MHz) XTALL to the PLL0 input
/*Set PLL0 to 240MHz with XOSC 40MHz*/
PLLDIG.PLL0DV.R = 0x50024030; //predefined PLL0 divider register
MC_ME.RUN_PC[0].R = 0xFE; /*Enable all modes for all peripherals using
ME_RUN_PC[0]*/
MC_ME.RUN_MC[0].B.XOSCON = 1; //Enable external oscillator
MC_ME.RUN_MC[0].B.PLL0ON = 1; //Enable PLL0 for RUN0 mode
MC_ME.RUN_MC[0].B.SYSCLK = 0x2; //source PLL0 PHI for RUN0 mode
//Mode transition to apply the PLL0 setup and set Normal mode with PLL running
MC_ME.MCTL.R = 0x40005AF0; //RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; //RUN0 Mode & Key
while(!MC_ME.GS.B.S_PLL0); //ME_GS Wait for PLL stabilization.
while(MC_ME.GS.B.S_MTRANS); //Waiting for end of transaction
/* ME_GS Check RUN0 mode has successfully been entered*/
while(MC_ME.GS.B.S_CURRENT_MODE != RUN0_MODE);
}
In your sample, Why CAN_CLK is set to 60 MHz not 40MHz?
I set CAN Clock to 60MHz, but I do not use this clock. I use 40MHz crystal as a protocol clock instead of CAN clock. It is recommended to use crystal, because it has lower jitter and it is more accurate than CAN clock.
auxiliary clock 7 should be SPT_CLK?
Yes, auxiliary clock 7 is SPT. I took my code from MPC5775K and I did not change the comment.
Regarding you lat post, you have to look at the MPC57xx MOTHERBOARD. I am attaching it to this post.
Regards,
Martin
