Problem with sending and receiving extended CAN frames

[pmrlcbtcphtzjdq]

I'm using the MPC5748G, and I am trying to send and receive an extended CAN frame and it doesn't work.

I modified the provided example and use two boards to check. Sending standard frames works - I have issues only with extended frames.

Does anybody have any suggestions on what could be wrong? Are there any extra registers I need to take into consideration?

The board that sends the CAN frame:

 uint32_t len = 60;
 uint8_t data_2[60] = "weewweewpcslksdlkmqwkmqwpmpdqwmcposkpokmdsapmodapodasmpoasd";
uitn32_t messageId = 2;

/* Set information about the data to be sent
     *  - 60 byte in length
     *  - Extendend message ID
     *  - Bit rate switch enabled to use a different bitrate for the data segment
     *  - Flexible data rate enabled
     *  - Use zeros for FD padding
     */
    flexcan_data_info_t dataInfo =
    {
            .data_length = len,
            .msg_id_type = FLEXCAN_MSG_ID_EXT,
            .enable_brs  = false,
            .fd_enable   = true,
            .fd_padding  = 0U
    };

    /* Configure TX message buffer with index TX_MSG_ID and TX_MAILBOX*/
    FLEXCAN_DRV_ConfigTxMb(INST_CANCOM1, mailbox, &dataInfo, messageId);

    /* Execute send non-blocking */
    FLEXCAN_DRV_Send(INST_CANCOM1, mailbox, &dataInfo, messageId, data);

The receiving board:

   /* Set information about the data to be received
     */
    flexcan_data_info_t dataInfo =
    {
            .data_length = 1U,
            .msg_id_type = FLEXCAN_MSG_ID_EXT,
            .enable_brs  = false,
            .fd_enable   = true,
            .fd_padding  = 0U
    };
    /* Configure RX message buffer with index RX_MSG_ID and RX_MAILBOX */
    FLEXCAN_DRV_ConfigRxMb(INST_CANCOM1, RX_MAILBOX, &dataInfo, RX_MSG_ID);

    /* clear the EACEN bit to recevie standard and extended IDE */
    CAN_0->CTRL2 |= CAN_CTRL2_EACEN(1);

    /* set the Mask to receive all the messages     */
    FLEXCAN_DRV_SetRxMbGlobalMask(INST_CANCOM1, 0 ,0);


     flexcan_msgbuff_t recvBuff;
     /* Start receiving data in RX_MAILBOX. */
     FLEXCAN_DRV_Receive(INST_CANCOM1, RX_MAILBOX, &recvBuff);


      /* wait for the successful transmission of data */
        if(FLEXCAN_DRV_GetTransferStatus(INST_CANCOM1, RX_MAILBOX) == STATUS_SUCCESS){
            PINS_DRV_TogglePins(PTH, 0x2000); //toggle PH13
}

[PetrS]

Hi,

does extended frames mean frame with extended ID or CAN FD frame?

 CAN_0->CTRL2 |= CAN_CTRL2_EACEN(1) sets EACEN bit, to clear it use CAN_0->CTRL2 &= ~CAN_CTRL2_EACEN(1);
If set it enables IDE and RTR bit compare with corresponding mask bits. 

Check used masking scheme (MCR[IRMQ), if set use individual masking registers.

If you cannot send a message check ECR/ESR1 registers.

BR, Petr

[BenMW]

Short question about the EACEN bit. If it's set to 1, there should be not comparision with the received IDE bit, like in the initial post, right?

From reference manual (page 1725):

If the CAN_CTRL2[EACEN] bit is negated, the IDE bit of Mailbox is always compared with the IDE bit of the incoming
frame.

[PetrS]

Hi,

as per the RM

PetrS_0-1630048930654.png

PetrS_1-1630048939260.png

If EACEN is set then bit30 of the mask register says if the IDE bit is don't care or not.
The same is valid for individual masking registers, if used.

BR, Petr

[BenMW]

Ok, thanks! After setting the RX mask with enabled bit 30, enter freeze mode, enable EACEN bit and exit freeze mode it works as expected