PCM_IAHB_BE1 - optimization

[Cristina_M]

In manual of MPC5777C Section 11.4, about PBRIDGE, says “an access that is larger than the target peripheral's data width will be decomposed to multiple, smaller accesses.

In Section 12.1.3, it is said that in Bus Bridge Configuration Register 1 (PCM_IAHB_BE1) is defined how is the bus gasket’s handling of pending transactions. The transactions can be read, write, burst read or burst write.

Questions:

What transactions are PCM_IAHB_BE1 configuring? Are they those smaller accesses mentioned in Section 11.4?

In this context, could transactions from different masters be mixed for optimization? Or despite the configuration of PCM_IAHB_BE1, the requisition of one master to one resource attached to PBRIDGE need to be finished (whether or not it is optimized) for another requisition from other master to the same resource to be initiated?

[davidtosenovjan · Accepted solution]

Instead of answering your question I would like to point out following erratum which actually prohibits setting of those bits:

[Cristina_M]

The errata is about the pending read transactions. How about the pending write transaction and burst read and burst write transactions. Could transactions from different masters be mixed for optimization? Or despite the configuration of PCM_IAHB_BE1, the requisition of one master to one resource attached to PBRIDGE need to be finished (whether or not it is optimized) for another requisition from other master to the same resource to be initiated?

[davidtosenovjan]

BRE_.. and BWE_.. are allowed to used (they are also enabled by default) but it is not related to pending transactions but all burst read/writes. These bits say whether burst accesses are used or not. Whether it is advantageous or not depends on the application.