Nexus does not bypass MPU on MPC5644A?

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Nexus does not bypass MPU on MPC5644A?

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EAlepins
Contributor V

Hi,

 

We are using the MPC5644A. We configure the MPU dynamically (the config changes very often) to allow the core to access only parts of the RAM. Indeed, there are multiple processes running on the core which have different privileges. We are having a debugging issue where we cannot look at variables from another process when we have set a breakpoint in a first process. This is because the MPU forbits that process to read variables of the other process. However, we would have expected the debugger to bypass access permissions!

 

There is no specific enable fields for the Nexus/JTAG in the MPU_RGDn.Word2 register. Indeed, the XBAR chapter in the RM seems to say that the core data port (M1) is used by the Nexus to access memory and so that the MPU cannot see the difference between the core and the debug module. Is that true? If so, isn't that a bad design? Is this solved in newer MCUs like MPC57xx?

 

Thanks.

Etienne

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Etienne,

yes, that's how it works on MPC56xx family. The MPU cannot differentiate between core and Nexus accesses to slave ports.

This has been solved on MPC57xx family - there are logical master IDs for Nexus, so we are able to set the privileges separately for Nexus and for core.

Regards,

Lukas

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Etienne,

yes, that's how it works on MPC56xx family. The MPU cannot differentiate between core and Nexus accesses to slave ports.

This has been solved on MPC57xx family - there are logical master IDs for Nexus, so we are able to set the privileges separately for Nexus and for core.

Regards,

Lukas

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EAlepins
Contributor V

Hi,

Ok. However, if I look at MPC5777C, the MPU indeed uses logical master ID, and according to Table 9-1. "XBAR master ports and logical master IDs", the IDs for Nexus is 8 or 9 (I don't know the difference). However, there are no M8RE/M8WE (or M9RE/M9WE) bits in the MPU_RGDn_WORD2 register. So how can we set read rights to the debug engine?

Thanks.

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Well, I can see that MPC5777C is an exception. This is the only device from MPC57xx family which has still MPU module. Other MPC57xx devices have SMPU module where it is possible to set rights separately for Nexus.

Lukas

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EAlepins
Contributor V

Hi,

So, that means that if on MPC5777C we have an OS which sets MPU rights to various processes, we'll still won't be able to read data of another process through our debugger when stopped in a process? This probably also mean if we do real-time non-intrusive Nexus reads without putting breakpoints, we won't be able to read any data at all since the process context switching takes places at a very fast rate (~ 2ms)?

Thanks.

Etienne

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

older MPU module (which is implemented also on MPC5777C) supports only 8 masters (0 - 7):

pastedImage_0.png

Logical master ID of Nexus on core0 is 8, on core1 it's 9. But only three wires are going to MPU module, so the MPU module can see Logical master ID only 0 or 1 even if access is coming from Nexus. MPU module is not able to recognize if it comes from core or Nexus.

So, the answer is: no, this is not supported on devices with MPU module. This is supported only by newer SMPU module.

Regards,

Lukas

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