Multicore MPC5748G FreeRTOS Example

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Multicore MPC5748G FreeRTOS Example

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Daniel_Wax
NXP Employee
NXP Employee

stanish‌ martinkovar

Im trying to put together a FreeRTOS example using all 3 MPC5748G cores.  Im having a tough time.  I am starting with the single core FreeRTOs example and duplicating it.  Trying to mimic the multicore interrupt example

All Id like to do is have one task scheduled to run in each core blinking an LED and be able to debug each core individually.

Ive added many things to the Project Properties Preprocessor defines like this:

-std=c99 -DSTART_FROM_FLASH -DCPU_MPC5748G -DTURN_ON_CPU0 -DTURN_ON_CPU1 -DTURN_ON_CPU2 -DDEBUG_SECONDARY_CORES USING_OS_FREERTOS

I get one of those "uncensored errors"

Has anyone an example of FreeRTOS running on each core?

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Daniel,

Freertos is not a multi-core OS. Each core can host own freertos instance but it will require more effort to implement it due to shared resources. I'm not aware of such example.

Regards,

Lukas

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Daniel_Wax
NXP Employee
NXP Employee

I forgot to mention this a for a strategic automotive OEM in my region

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Daniel Wax | Field Applications Engineer Automotive

NXP Semiconductors

411 E Plumeria Dr

San Jose, CA 95134

office: 408-518-5533

mobile: 408-981-9220

daniel.wax@nxp.com<mailto:daniel.wax@nxp.com>

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi ovidiu.alexandru‌,

maybe you could help. Do you know if anyone tried that? Or what is needed effort to do that?

Thanks,

Lukas

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Daniel_Wax
NXP Employee
NXP Employee

Thanks Lukas. I understand it’s not a multi core OS. Was hoping to load three instances. One free RTOS for each core. Each instance also to load from an separate 256k flash partition

SENT FROM PHONE

Daniel Wax | Field Applications Engineer Automotive

NXP Semiconductors

411 E Plumeria Dr

San Jose, CA 95134

office: 408-518-5533

mobile: 408-981-9220

daniel.wax@nxp.com<mailto:daniel.wax@nxp.com>

All types of technical support (Schematic review, layout review, software review, hardware board and software) provided

by NXP Field application team are subject to NXP's general Terms and Conditions unless superseded by a direct contract.

The information contained in this message is confidential and may be legally privileged. The message is intended solely for the addressee(s). If you are not the intended recipient, you are hereby notified that any use, dissemination, or reproduction is strictly prohibited and may be unlawful. If you are not the intended recipient, please contact the sender by return e-mail and destroy all copies of the original message.

Unless otherwise recorded in a written agreement, all sales transactions by NXP Semiconductors are subject to our general terms and conditions of commercial sale<http://www.nxp.com/about/our-terms-and-conditions-of-commercial-sale:TERMSCONDITIONSSALE?fsrch=1&sr=1&pageNum=1>.

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