MPC5777M: How to ensure shared memory coherency

[alainfelici]

Hello all, 

We are writing an application requiring shared memory berween core and cache enabled (for perfomance issue). 

The memory will be updated by two ways: The classical one (store memory) and DMA. 

I don't know how to ensure cache coherency in these cases. Is someone can help us?

Thanks for you help. 

Alain 

[petervlna]

Hello,

This microcontroller do not implement cache coherency unit.

So you have to:

1.) For resource sharing you can use XBAR settings to prioritize accesses. So DMA won't access to memory while it is used by core and vice versa.

2.) Use SMPU to disable caching on memory area share between core and DMA. This is common case.

Peter