MPC5777C - Questions about the PRAMC (late-write buffer and bursts)

[MatheusFranklin]

Hello!

I have two questions about the PRAMC:

1 - What happens when the caches of different cores request different data that belongs to the same cache line? The XBAR requests two bursts wrapped in a different order or the SRAM services the same burst to both cores and the XBAR sends a copy of the burst to each core?

If the XBAR sends the same burst to both cores, in which order are the words in this burst wrapped? The word requested from which core will be serviced first in the burst request?

2 - When is the late-write buffer emptied? When it is full or when it is already full and the PRAMC tries to put more data in it? The question that I am trying to answer is if there is the possibility of a core performing a write operation and, because of the late-write buffer being full, the core write latency is increased with the entire latency of the late-write buffer being emptied.

Best regards,

Matheus

[davidtosenovjan · Accepted solution]

1) Not sure what you mean by different data. I suppose you mean ‘different address’ belonging to the same line. Also I suppose you are discussing situation when other ways of cache are full.

1a) As you already know, Internal SRAM is split into two halves, each accesses over different port:

PRAMC_0 - Slave Port 2 - Address[31:18] = 0100_0000_0000_00b

PRAMC_1 - Slave Port 4 - Address[31:18] = 0100_0000_0000_01b

Both accesses may run in parallel, there is no issue.

1b) If both accesses goes over same port, firstly started access is executed first (if both triggered simultaneously then started according priority). Burst access cannot be interrupted, it is locked transfer with longest access time. Firstly burst access from one core happens and then burst access from another core.

2) RAM says “In the case of back-to-back writes, the write may be forced to bypass the late-write buffer and instead be stored directly, precisely in the RAM.” In other words, if late write buffer is full and another write happens, this write is processed first and then late-write buffer is emptied.