Hey,
MPC5777C has a symmetrical dual-core. For my application, tasks have been divided into two parts, as sequential and periodic ones. Because of this, Core0(Master) has to have control over Core1 (Slave). So, my application needs inter-processor communication, to carry information between slave and master cores.
SIPI :
There is a Serial Interprocessor Interface (SIPI) peripheral in the MPC5777C peripheral set, which is built onto the LVDS base. I thought that could be used for communication between the cores, but I see that need a pinout configuration for this module.
-Is this module only working for different devices?
Inter-core communication Peripheral Support :
- Also, I wonder that is there any peripheral or commonly used method to use for interprocessor communication?
Shared RAM:
As a last option, MPC5777C has a shared RAM, which I separated as follows.
***************************************
CORE0 RESERVED-32K
***************************************
CORE0 SRAM-64K
***************************************
SHARED RAM 1 - 32K
***************************************
SHARED RAM 2 - 32K
***************************************
CALIBRATION-256K
***************************************
CORE1 RESERVED-32K
***************************************
CORE1 SRAM-64K
***************************************
As a last option, inter-core communication will be obtained by using shared RAM. There are two approaches in my mind,
First: Multiple channel DMA's and their interrupts can be configured for this purpose.
Second: The handler function for each core can be created, for dedicated RX - TX buffer areas in shared RAM. Every core calls the other one's handler function after filling the RX buffer of the other core.
- Is there any way to disable the cache, only for the specific part of the RAM?
Best Regards
Ege
