[MPC5777C] How can i cause exception error or unidentified interrupt?

[jongminna]

Hi, Dear

Our development environment here

MCU : MPC5777C

OS : ETAS RTA OS

Compiler : Windriver diab 5.9.4

I want to exception handler test, so I have to make some kind of exception error.

Refer to e200z760RM(315page), MPC5777C has Machine check(IVOR1) and Program(IVOR6).

I don't know that what i have to do for causing a exception error.

In specific, I want to test "Illegal instruction exception", "Data cache parity error" and Exception handler which is cased by specified error.

In other words, I want to fault injection method above them.

Please let me know what i have to do.

Thank you.

[simeen]

Hello All,

I am stuck on how to inject cache related faults in the system (Arm r52). I can see there is a way to inject faults in CRS using EIM, is there something similar to inject faults in Cohorts as well? If yes, please can you tell me on how to test by injecting cache fault and checking the output.

[gvictorio]

Hello Jongmin,

Have you tried the instruction se_illegal? that seems to be exactly what you need for the illegal instruction exception.

Other ideas may be:

• Try to write to a register of a peripheral that is not enabled.
• Try to write to an reserved/invalid memory address

For the parity error, I'm not sure if trying to read from a RAM location that has not been initialized (never written) would do the trick.

[jongminna]

Thank you for your answer.

I have solved this question.

First of all, For the illigal insturction error, I try to execute instruction at the unused area.. Then exception error is arised.

Cache parity error is arised by cache controller, cache error injection.

Is it right solution?

[lukaszadrapa]

Hi,

when you access memory (either instruction fetch or data load/store) and bus error occurs (unimplemented memory, ECC error...) then IVOR1 is triggered regardless of MSR[ME].

Read the chapter "7.6.2 Machine Check Interrupt (IVOR1)" in core reference manual for more details:

http://www.nxp.com/files/32bit/doc/ref_manual/e200z760RM.pdf

If a bus error does not occur during instruction fetch but invalid opcode is loaded (or se_illegal is used) then IVOR6 is triggered.

Yes, it is possible to inject the error to cache:

Cache errors will trigger IVOR1 exception. See the tables:

Table 7-10. Error Report Machine Check Exceptions

Table 7-11. Asynchronous Machine Check Exceptions

... in core reference manual.

Regards,

Lukas