MPC5777C Flash Crash Problem

[Ada_Lovelace]

Hi , All

I have the problem about Flash of MPC5777C, when ECU power down,and power on again,the code crashs, I debug the memory view, it shows the data in the memory did not show the value, it shows the "?".

I guess the it may cause by writing Flash,but I read the statue about Flash before the power down, it returns ok, so what should I do to solve the problem?

It does not happen every time,it happens occasionally,

Please help me,thank you.

[lukaszadrapa]

Hi,

this is caused by double bit ECC error. Generally, such error can appear when:

1. You program a double word which is not fully erased

2. Erase or program operation is terminated by unexpected reset

3. Too many erase/program cycles have been performed (see the datasheet for minimal and typical number of cycles).

In this case, it seems to be the first reason. To recover, it's necessary to erase the flash. To avoid this situation, check if a double word you are going to program is really fully erased.

And if you are programming the flash in runtime, so there's a risk that device is reset during program/erase operation, it's necessary to handle IVOR1 exception appropriately, so you can erase affected block(s) to recover.

Regards,

Lukas

[Ada_Lovelace]

Hi, Lucas

How to handle IVOR1 exception appropriately? It means that I need to erase flash when it runs into the IVOR1 interrupt?

But  I  think it works when the ECU power on, the data of the flash will lost, I need the data of the flash when it power on.

Or it has a method to avoid the ECC error, or when  the flash writes failed, it can restart writing flash again until the flash finished ,and then  power off?

Regards,

Ada

[lukaszadrapa]

Hi Ada,

“It means that I need to erase flash when it runs into the IVOR1 interrupt?”

- In short, yes. The best practice is to use special function for reading of data flash blocks which are updated in runtime. If IVOR1 occurs, you can simply check the address of instruction which caused the error (core register MCSRR0). If the address fall withing address range of that function and if it was read bus error on data load (core register MCSR), you know the exception was caused by reading of corrupted data flash. Just set some global flag to inform the function and return from IVOR1 handler. Notice it’s necessary to update return address in MCSRR0 because it still points to instruction which caused the error. If you don’t do that, the instruction would be executed again and the IVOR1 would be triggered again. For more details, take a look at:

https://www.nxp.com/docs/en/application-note/AN5200.pdf

https://www.nxp.com/docs/en/application-note-software/AN5200SW.zip

https://www.nxp.com/docs/en/application-note/AN4648.pdf

https://www.nxp.com/docs/en/application-note/AN13067.pdf

There’s no method that would try to write the flash until it’s successful. This must be solved on application level.

Good idea is to check the data flash after each reset. You can read your data flash blocks word by word to see if there are ECC errors and then take appropriate action (this is application dependent).

You can use DMA for this to save time. In this case no IVOR1 is triggered, but error flag is set in DMA.

 Regards,

Lukas

[Ada_Lovelace]

Hi,Lucas

When I met the problem, I do the change about Cache

I write the code when it is init,will it affect the flash ，or cause the ECC error?

I reference the code about  AN5191 pdf.

[lukaszadrapa]

Hi Ada,

I'm sorry for delayed response, I was out of office last week.

Enabled cache memory can cause only data incoherence, not ECC errors.

For example, let's assume this situation - you read some data from flash memory (that means it's loaded to cache at the same time). If you erase that flash block now, the cache is not informed about this operation. So, if you read the cached area now, you will read old content of flash. It's responsibility of user to invalidate the cache in this situation or you can configure that area as cache inhibited.

There's hardware cache coherency unit on this device but it works only between the cores and DMA.

Regards,

Lukas

[Ada_Lovelace · Accepted solution]

Hi,Lukas

I have solved the problem:

Dcache  bit DCWM, I choose  copyback mode, it will cause flash error.So I change the mode to writethrough mode,it works.