MPC5746C Flash Initialization Error

[cholland]

Hi,

Every time the processor boots up, I get an RGM.DES.B.F_SWT0.RES = 1.

This means that there is/was a Flash Initialization Failure.

I am trying to investigate the problem further.

My problem is that the failure is kind of vague. I don't know what it means exactly.

I am wondering if it is trying to initialize a certain block?

Is there some sort of read/write error?

Would it be in the Initialization script 57xx_flash.ld?

I have seen code out there that does a flash check. It is written for another processor.

Perhaps I could modify it to check the flash on the MPC5746C?

Thank you,

[petervlna]

Hello,

I will try to bring some light into this error.

The flash is initialized during reset sequence (It is complex process)

This is done during rest phase 1:

The flash initialization is guarded by SWT0 to ensure that it has not been stuck. As user has no possibility to control execution flow during reset sequence.

Now the question is, if you are using your own design of the board or the EVB from NXP.

Because this looks like serious problem with micro or its flash power supply.

Is this seen on more products or just on one?

regards,

Peter

[cholland]

Hi Peter,

Glad to hear you!

This is an EVB from NXP. (MPC5748G EVB)

It happens on every MPC5746C I try.

I was go to try to investigate it further, because it does seems strange.

I understand the process a bit, but It confuses me.

If I do a Functional Reset with Soft Reset enabled, (RGM.FESS.B.SS_SOFT_FUNC = 1), I get this error every time.

I believe it's supposed to skip to phase 3 of the boot process, but it doesn't seem to work and this happens.

If I just do a plain old (RGM.FESS.B.SS_FCU_SHORT) functional reset, it skips to phase 3.

I think the Soft Reset is a Soft Destructive Reset?

It says Soft Reset is a Destructive Reset in the RGM.DES register. (F_SOFT_DEST)

You mentioned it once in one of your other posts. (To someone else)

So this is what is causing my troubles. 

Thanks for your help.

[petervlna]

Hello Christopher,

I think the Soft Reset is a Soft Destructive Reset?

There is not such thing as Soft destructive reset. If the reset is destructive, the device starts from reset Phase1.

It says Soft Reset is a Destructive Reset in the RGM.DES register. (F_SOFT_DEST)

This is software [SOFT] destructive reset. It is caused by mode transition to mode 0xF

If I do a Functional Reset with Soft Reset enabled, (RGM.FESS.B.SS_SOFT_FUNC = 1), I get this error every time.

I believe it's supposed to skip to phase 3 of the boot process, but it doesn't seem to work and this happens.

Setting FESS[SOFT_FUNC] will do software (triggered by ME module via mode transition to mode 0) functional short reset.

Yes, this will skip reset phase 3. But only on software reset. This means there is no need to initialize flash, as it is in power domain which will not loose power on this kind of reset.

If I just do a plain old (RGM.FESS.B.SS_FCU_SHORT) functional reset, it skips to phase 3.

FCU_SHORT, you mean FCCU_SHORT? this device do implement FCCU instead of old FCU.

But still, I see no reason for SWT0 to run if the device is reset to phase 3. And personally I never seen flash initialization failure before on NXP evaluation board.

It seems to me that it can be real SWT timeout (unhanded in your code). Maybe in some interrupt where you call software reset our SWT will run out and call reset before software reset. It is hard to say.

Try to disable the SWT0 in assembly startup, right after power on reset.

And see if the fault is gone.

Or just run one of our examples, to see if it still persists.

https://community.nxp.com/docs/DOC-329623#MPC5748G 

best regards,

Peter

[cholland]

Peter,

I am getting the same response with example Example_MPC5748G_Overlay_SRAM_Overlay_Flash_config_S32DS

The Startup.s in my project and the example are both disabling the SWT. (I stepped through the code initially, so it is working)

;#****************************** Turn off SWTs ********************************

#define DISABLE_SWT0 1 /*Added to ensure SWT0 is disabled. Should not happen anyways. It should just skip to phase 3 */
#if defined(DISABLE_SWT0)
;#SWT0
e_lis r4, 0xFC05
e_or2i r4, 0x0000

e_li r3, 0xC520
e_stw r3, 0x10(r4)

e_li r3, 0xD928
e_stw r3, 0x10(r4)

e_lis r3, 0xFF00
e_or2i r3, 0x010A
e_stw r3, 0(r4)
#endif

This is the break point after a functional reset. 

I just wanted to show you the exact code that I am using.

P.S. FCU_SHORT, you mean FCCU_SHORT? this device do implement FCCU instead of old FC

Yes. It was a typo

[petervlna]

Hi,

When I execute it from code I will get reset from PHASE3 and no SWT set.

Also when I execute it from debugger I see same behavior.

And I also see the correct source of reset which is SW reset.

But you seeing different reset type DES  [F_SWT0] from the one you are triggering.

If you sent me the compiler project I can check it here. Output file is enough.

Another thing is are you clearing the FES and DES registers after reset? So you can always track latest reset source?

regards,

Peter

[cholland]

Peter,

I found the problem.

The example doesn't do any peripheral clock generation InitPeriClkGen().

When I remove the function void SYS_InitPeriClkGen(void), it works fine.

I have tried changing the order of the functions, but it doesn't seem to have any effect.

Thanks for your help,

void SYS_clk_init(void)
{
MC_CGM.AC5_SC.B.SELCTL = 1; //Connect FXOSC to the FMPLL input.

//Set FMPLL to MHz with 16 MHz FXOSC reference.
PLLDIG.PLLDV.R = 0x06021050; //PREDIV = 1, MFD = 80, RFDPHI = 3, RFDPHI1 = 3
PLLDIG.PLLFD.R = 0x00000000; //PLL fractional numerators
PLLDIG.PLLCAL3.R = 0x00004000; //PLL fractional denominator //MFDEN = 1

//Turn on clock sources and select system clock source
MC_ME.RUN_MC[0].R = 0x001301F2; //Configure RUN0 mode settings with sysclk FMPLL_PHI0 (64 MHz).
//MC_ME.RUN_MC[0].B.MVRON = 1;
//MC_ME.RUN_MC[0].B.FLAON = 3;
//MC_ME.RUN_MC[0].B.SXOSCON = 1;
//MC_ME.RUN_MC[0].B.SIRCCON = 1
//MC_ME.RUN_MC[0].B.PLLON = 1;
//MC_ME.RUN_MC[0].B.FXOSCON = 1;
//MC_ME.RUN_MC[0].B.FIRCON = 1;
//MC_ME.RUN_MC[0].B.SYSCLK = 1;

//Configure the oscillator divided clocks
SIRC.CTL.R = 0x00000011; //SIRC_DIV_CLK is SIRC divided by 1 (0.128 MHz).
SIRC.CTL.B.SIRCS = 1; //Should be the only one set. No ideal why they do 0x...11 and get the value they do?
FIRC.CTL.R = 0x00000011; //FIRC_DIV_CLK is FIRC divided by 1 (16 MHz).
FIRC.CTL.B.FIRCS = 1; //Should be the only one set. No ideal why they do 0x...11 and get the value they do?

SXOSC.CTL.B.OSCDIV = 0x00; //SXOSC_DIV_CLK is SXOSC divided by 1 (0.032 MHz).
FXOSC.CTL.B.OSCDIV = 0x00; //FXOSC_DIV_CLK is FXOSC divided by 1 (16 MHz).

MC_ME.RUN_PC[0].R = 0x000000FE; //Enable peripherals to run in all modes

//Mode transition to RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; //Enter RUN0 mode & Key
MC_ME.MCTL.R = 0x4000A50F; //Enter RUN0 mode & Inverted Key
while(MC_ME.GS.B.S_MTRANS); //Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 0x4); //Verify RUN0 is the current mode

}

void SYS_InitPeriClkGen(void)
{
MC_CGM.SC_DC0.R = 0x80000000; //S160 at system clock divided by 0 (160 MHz).//DE = 1, DIV = 0
//MC_CGM.SC_DC0.B.DE = 1;
//MC_CGM.SC_DC0.B.DIV = 0;

MC_CGM.SC_DC1.R = 0x80010000; //S80 at system clock divided by 2 (80 MHz). //DE = 1, DIV = 1
//MC_CGM.SC_DC1.B.DE = 1;
//MC_CGM.SC_DC1.B.DIV = 1;

MC_CGM.SC_DC2.R = 0x80030000; //S40 at system clock divided by 4 (40 MHz). //DE = 1, DIV = 3
//MC_CGM.SC_DC2.B.DE = 1;
//MC_CGM.SC_DC2.B.DIV = 3;

MC_CGM.SC_DC5.R = 0x01000000; //FS80 at system clock divided by 1 (80 MHz). //DE = 1, DIV = 0
//MC_CGM.SC_DC5.B.DE = 1;
//MC_CGM.SC_DC5.B.DIV = 0;

MC_CGM.AC2_SC.R = 0x01000000; //ENET timers use TXD_CLK/RMII_CLK as source (50 MHz). //SELCTL = 1
//MC_CGM.AC2_SC.B.SELCTL = 1;

MC_CGM.AC3_SC.R = 0x01000000; //HSM TRNG uses FXOSC as source (16 MHz). //SELCTL = 1
//MC_CGM.AC3_SC.B.SELCTL = 1;

MC_CGM.AC5_SC.R = 0x01000000; //FMPLL uses FXOSC as source (16 MHz). //SELCTL = 1
//MC_CGM.AC5_SC.B.SELCTL = 1;

MC_CGM.AC6_SC.R = 0x02000000; //CLKOUT0 uses as source PLL_CLKOUT1 (64 MHz.) //SELCTL = 2
//MC_CGM.AC6_SC.B.SELCTL = 2;

MC_CGM.AC6_DC0.R = 0x80000000; //Divide CLKOUT0 source by 1 (64 MHz).//DE = 1, DIV = 0
//MC_CGM.AC6_DC0.B.DE = 1;
//MC_CGM.AC6_DC0.B.DIV = 0;

MC_CGM.AC8_SC.R = 0x00000000; //SPI0 source is F40 (16 MHz). //SELCTL = 0
//MC_CGM.AC8_SC.B.SELCTL = 0;

MC_CGM.AC9_SC.R = 0x00000000; //FlexCAN0 source is FS80 (16 MHz). //SELCTL = 0
//MC_CGM.AC9_SC.B.SELCTL = 0;

MC_CGM.CLKOUT1_SC.R = 0x0E000000; //CLKOUT1 uses as source PLL_CLKOUT1 (64 MHz). //SELCTL = 0xE
//MC_CGM.CLKOUT1_SC.B.SELCTL = 0xE;

MC_CGM.CLKOUT1_DC.R = 0x80000000; //CLKOUT1 uses as source PLL_CLKOUT1 (64 MHz).//DE = 1, DIV = 0
//MC_CGM.CLKOUT1_DC.B.DE = 1;
//MC_CGM.CLKOUT1_DC.B.DIV = 0;
}

[petervlna]

Hi,

As I have said, I never seen before real flash initialization failure on our EVB. So it is SW issue, where your SWT is triggering reset.

Otherwise it will be HW design failure or micro failure which is (very rare).

regards,

Peter

[cholland]

Hello?

[cholland]

Peter,

I found the problem.

The example doesn't do any peripheral clock generation InitPeriClkGen().

When I remove the function void SYS_InitPeriClkGen(void), it works fine.

I have tried changing the order of the functions, but it doesn't seem to have any effect.

Thanks for your help,

void SYS_clk_init(void)
{
MC_CGM.AC5_SC.B.SELCTL = 1; //Connect FXOSC to the FMPLL input.

//Set FMPLL to MHz with 16 MHz FXOSC reference.
PLLDIG.PLLDV.R = 0x06021050; //PREDIV = 1, MFD = 80, RFDPHI = 3, RFDPHI1 = 3
PLLDIG.PLLFD.R = 0x00000000; //PLL fractional numerators
PLLDIG.PLLCAL3.R = 0x00004000; //PLL fractional denominator //MFDEN = 1

//Turn on clock sources and select system clock source
MC_ME.RUN_MC[0].R = 0x001301F2; //Configure RUN0 mode settings with sysclk FMPLL_PHI0 (64 MHz).
//MC_ME.RUN_MC[0].B.MVRON = 1;
//MC_ME.RUN_MC[0].B.FLAON = 3;
//MC_ME.RUN_MC[0].B.SXOSCON = 1;
//MC_ME.RUN_MC[0].B.SIRCCON = 1
//MC_ME.RUN_MC[0].B.PLLON = 1;
//MC_ME.RUN_MC[0].B.FXOSCON = 1;
//MC_ME.RUN_MC[0].B.FIRCON = 1;
//MC_ME.RUN_MC[0].B.SYSCLK = 1;

//Configure the oscillator divided clocks
SIRC.CTL.R = 0x00000011; //SIRC_DIV_CLK is SIRC divided by 1 (0.128 MHz).
SIRC.CTL.B.SIRCS = 1; //Should be the only one set. No ideal why they do 0x...11 and get the value they do?
FIRC.CTL.R = 0x00000011; //FIRC_DIV_CLK is FIRC divided by 1 (16 MHz).
FIRC.CTL.B.FIRCS = 1; //Should be the only one set. No ideal why they do 0x...11 and get the value they do?

SXOSC.CTL.B.OSCDIV = 0x00; //SXOSC_DIV_CLK is SXOSC divided by 1 (0.032 MHz).
FXOSC.CTL.B.OSCDIV = 0x00; //FXOSC_DIV_CLK is FXOSC divided by 1 (16 MHz).

MC_ME.RUN_PC[0].R = 0x000000FE; //Enable peripherals to run in all modes

//Mode transition to RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; //Enter RUN0 mode & Key
MC_ME.MCTL.R = 0x4000A50F; //Enter RUN0 mode & Inverted Key
while(MC_ME.GS.B.S_MTRANS); //Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 0x4); //Verify RUN0 is the current mode

}

void SYS_InitPeriClkGen(void)
{
MC_CGM.SC_DC0.R = 0x80000000; //S160 at system clock divided by 0 (160 MHz).//DE = 1, DIV = 0
//MC_CGM.SC_DC0.B.DE = 1;
//MC_CGM.SC_DC0.B.DIV = 0;

MC_CGM.SC_DC1.R = 0x80010000; //S80 at system clock divided by 2 (80 MHz). //DE = 1, DIV = 1
//MC_CGM.SC_DC1.B.DE = 1;
//MC_CGM.SC_DC1.B.DIV = 1;

MC_CGM.SC_DC2.R = 0x80030000; //S40 at system clock divided by 4 (40 MHz). //DE = 1, DIV = 3
//MC_CGM.SC_DC2.B.DE = 1;
//MC_CGM.SC_DC2.B.DIV = 3;

MC_CGM.SC_DC5.R = 0x01000000; //FS80 at system clock divided by 1 (80 MHz). //DE = 1, DIV = 0
//MC_CGM.SC_DC5.B.DE = 1;
//MC_CGM.SC_DC5.B.DIV = 0;

MC_CGM.AC2_SC.R = 0x01000000; //ENET timers use TXD_CLK/RMII_CLK as source (50 MHz). //SELCTL = 1
//MC_CGM.AC2_SC.B.SELCTL = 1;

MC_CGM.AC3_SC.R = 0x01000000; //HSM TRNG uses FXOSC as source (16 MHz). //SELCTL = 1
//MC_CGM.AC3_SC.B.SELCTL = 1;

MC_CGM.AC5_SC.R = 0x01000000; //FMPLL uses FXOSC as source (16 MHz). //SELCTL = 1
//MC_CGM.AC5_SC.B.SELCTL = 1;

MC_CGM.AC6_SC.R = 0x02000000; //CLKOUT0 uses as source PLL_CLKOUT1 (64 MHz.) //SELCTL = 2
//MC_CGM.AC6_SC.B.SELCTL = 2;

MC_CGM.AC6_DC0.R = 0x80000000; //Divide CLKOUT0 source by 1 (64 MHz).//DE = 1, DIV = 0
//MC_CGM.AC6_DC0.B.DE = 1;
//MC_CGM.AC6_DC0.B.DIV = 0;

MC_CGM.AC8_SC.R = 0x00000000; //SPI0 source is F40 (16 MHz). //SELCTL = 0
//MC_CGM.AC8_SC.B.SELCTL = 0;

MC_CGM.AC9_SC.R = 0x00000000; //FlexCAN0 source is FS80 (16 MHz). //SELCTL = 0
//MC_CGM.AC9_SC.B.SELCTL = 0;

MC_CGM.CLKOUT1_SC.R = 0x0E000000; //CLKOUT1 uses as source PLL_CLKOUT1 (64 MHz). //SELCTL = 0xE
//MC_CGM.CLKOUT1_SC.B.SELCTL = 0xE;

MC_CGM.CLKOUT1_DC.R = 0x80000000; //CLKOUT1 uses as source PLL_CLKOUT1 (64 MHz).//DE = 1, DIV = 0
//MC_CGM.CLKOUT1_DC.B.DE = 1;
//MC_CGM.CLKOUT1_DC.B.DIV = 0;
}

[cholland]

Peter,

>>Another thing is are you clearing the FES and DES registers after reset? So you can always track latest reset source?

No. I was not doing that. When I cleared the FES and DES registers, the issue no longer appears, in the example anyways.

The issue still occurs in my project.

>>It seems to me that it can be real SWT timeout (unhanded in your code). Maybe in some interrupt where you call software reset our SWT will >>run out and call reset before software reset. It is hard to say.

Well, back to square 1. I will try to make my project more like the example and see if I can track the issue.

I'll post back when and if I find anything.

Thanks a lot for your help.

Stay safe my friend.

Regards,