Recently, I have been trying to change the SRAM of MPC5744P and have found some issues. I hope someone can help me solve them. The problem is that after completing initialization, I receive messages through the CAN bus in a dead loop and change the data of the SRAM when the message is valid and triggered. The code for changing SRAM is as follows:
uint8_t i;
for(i=0;i<32;i++)
{
*(uint8_t *)(0x40000000+i) = 0xFF;
}
When I changed the SRAM at the above address(0x40000000), MPC5744P experienced a reset, and I believe it triggered the SRAM ECC. Of course, the SRAM part I modified was not used by the system. I cleared the 1KB area of SRAM starting from 0x4000000 by modifying the connection file. Code below:
/* Entry Point */
ENTRY(_start)
/* define heap and stack size */
__HEAP_SIZE = 0 ;
__STACK_SIZE = 4096 ;
SRAM_SIZE = 383K;
/* Define SRAM Base Address */
SRAM_BASE_ADDR = 0x40000000;
/* Define CPU0 Local Data SRAM Allocation */
LOCALDMEM_SIZE = 64K;
/* Define CPU0 Local Data SRAM Base Address */
LOCALDMEM_BASE_ADDR = 0x50800000;
MEMORY
{
flash_rchw : org = 0x00FA0000, len = 0x4
cpu0_reset_vec : org = 0x00FA0004, len = 0x4
reboot_start_check : org = 0x00FA0100, len = 0x10
m_text : org = 0x00FA0400, len = 190K
reboot_end_check : org = 0x00FCFC00, len = 0x10
m_data : org = 0x40000400, len = 383K
local_dmem : org = 0x50800000, len = 64K
}
Although I have freed up some SRAM, it will still reset after modifying the data for that address. So I turned off the SRAM ECC initialization in the startup file and found that the reset phenomenon disappeared. Here is the code I blocked:
;#***************************** Initialise SRAM ECC ***************************/
;# Store number of 128Byte (32GPRs) segments in Counter
e_lis r5, __SRAM_SIZE@h # Initialize r5 to size of SRAM (Bytes)
e_or2i r5, __SRAM_SIZE@l
e_srwi r5, r5, 0x7 # Divide SRAM size by 128
mtctr r5 # Move to counter for use with "bdnz"
;# Base Address of the internal SRAM
e_lis r5, __SRAM_BASE_ADDR@h
e_or2i r5, __SRAM_BASE_ADDR@l
;# Fill SRAM with writes of 32GPRs
sram_loop:
e_stmw r0,0(r5) # Write all 32 registers to SRAM
e_addi r5,r5,128 # Increment the RAM pointer to next 128bytes
e_bdnz sram_loop # Loop for all of SRAM
My question is why writing SRAM through addresses and pointers triggers ECC, or other issues are causing my situation to occur. What if I want to enable ECC for SRAM and manually modify SRAM?
