MPC5744P In power module, does someone have a recommended tolerant value for monitoring band gap voltage of 1.2V? 1% or else?

[shawnzhao]

For the safety, the band gap voltage of 1.2V need to be monitored. Does someone have the recomended value to consider the power module is safe?

[petervlna]

Hi,

There is an AN note dealing with ADC self tests. I recommend you to read it.

MPC5744P ADC SELF TEST

Peter

[shawnzhao]

Thanks, Peter!

This is a useful document.

[petervlna]

Hi,

This voltage is internally monitored on MPC5744P.

When internal LVD (low voltage detector) detects a violation of desired thresholds it triggers destructive reset.

The reset source is stored in RGM [DES] register.

Peter

[shawnzhao]

Hi Peter,

Thansks for your answer!

This is another measure to monitor the Core supply to keep Power module safe.

Assumption: [SM_204] It is assumed that the ADC's are used to monitor the bandgap reference voltage of the PMC. [end]  page-56 from MPC5744PSM

Bandgap reference voltage links to the ADC0 Channel 10 internally. We want to monitor this voltage which is 1.2V by ADC, not the Core supply, so we want to set the threshold for monitoring. But now we don't know which threshold is suitable. So do you have a recommended value?

[petervlna · Accepted solution]

In general the bandgap voltage is measured via ADC self-test mechanism.

I recommend you to read reference manual chapter 36.5.10.2 Self test (Quick-Check/Safety mode).

In the supply self-test algorithm, the band gap is measured with regard to the reference

voltage (Vrh) in step 0. The result is capable of catching mismatches between them. Step

1 measures the supply with regard to reference (Vrh), and the result is taken to do a ratio

(Vdda/Vbg). If the band gap voltage remains within +/-1.25% of its ideal value of 1.2 V,

then by setting appropriate values of THRH and THRL in watchdog registers, the ADC

self-test can catch more than 4% variation in supply and reference faithfully.

[shawnzhao]

Hi Peter,

Thanks!

I study the ADC self test chapter about the band gap measure. It is sure it will monitor the band gap by the hardware, I could get the monitoring result from the register STSR1[ERR_S0]. Now I have two questions.

1. How to set the THRL? It said that "A negative value is expected in this field" . As my understand, it may be 1.2V*(100%-1.5%) for THRL, and 1.2V*(100%+1.5%) for THRH. How to set a negative value?

2. Can I do ADC self test periodically? Because band gap need to be monitered at least once per FTTI.

Above picture from Panther_FMEDA_report_part2_1.1.pdf, the ADC self test could cover this requirement?