MPC5744 Register Protection

[Jamber_H]

Hi, 

Some modules, such as MC_ME, can set the Register Protection, as shown in the fig.1, but some other modules, such as CMU_0, can't use this function, and it's soft lock bit not exist, as shown in the fig.2.

Another question, in the Protected Registers list, why different modules have same Base Address? as shown in the fig.3, CMU0 and CMU1 has a same Base Address 0xFBFB0200, is it correct?

 

 

 

[mayank22]

Hi Peter ,

These are the Modules on which I am implementing Locking mechanism under Register Protection for MPC5746C.  - 

    0xFFFB0140, /* CMU------------*/

    0xFFFB0040, /* FXOSC----------*/

    0xFFFB0180, /* MC_CGM --------*/

    0xFFFB8000, /* MC_ME ---------*/

    0xFFFA8000, /* MC_RGM --------*/

    0xFFF50000, /* MEMU_0 -------*/

    0xFFFB0080, /* PLLDIG --------*/

    0xFFFA0400, /* PMCDIG --------*/

    0xFFFC0000, /* SIUL2 ---------*/

    0xFFFB0100, /* SXOSC ---------*/

    0xFFF9C000 /* LPU_CTL -------*/

what I am facing that some module GCR and SLB bit are throwing bus error if tried to access. similarly for those module it is soft/hard lock is working , I can still face the same problem for few registers set. I am attaching two samples of screen shots where first one is working and you can see all register/mirror/SLB and GCR addresses enabled while in second case SLB &GCR throws error if try to use them. 

what could be the reason for this different behavior ? if u want I can attach my manual calculations for register/mirror/SLB and GCR addresses.

[petervlna]

Hello,

To make it easy, here are macros which can be used for configuring register protection.

/*PowerPC*/

/*-----------------------------------------------------------------------------------------------------------*/
#define REGPROTPPMIRROR 0x2000
#define REGPROTPPSLBR 0x3800
#define REGPROTPPGCR 0x3FFC

#define WRITE_WITH_LOCK_PP_8BIT(registeraddress, value)   
#define WRITE_WITH_LOCK_PP_16BIT(registeraddress, value)   
#define WRITE_WITH_LOCK_PP_32BIT(registeraddress, value)   

#define GET_SOFTLOCK_PP(modulebaseaddress, registeraddress, value)
#define CLR_SOFTLOCK_PP_32BIT(modulebaseaddress, registeraddress)
#define CLR_SOFTLOCK_PP_16BIT(modulebaseaddress, registeraddress)
#define CLR_SOFTLOCK_PP_8BIT(modulebaseaddress, registeraddress)

#define SET_SOFTLOCK_PP_32BIT(modulebaseaddress, registeraddress)
#define SET_SOFTLOCK_PP_16BIT(modulebaseaddress, registeraddress)
#define SET_SOFTLOCK_PP_8BIT(modulebaseaddress, registeraddress)

#define SET_HARDLOCK_PP(modulebaseaddress)
#define USER_ACCESS_FORBIDDEN_PP(modulebaseaddress)
#define USER_ACCESS_ALLOWED_PP(modulebaseaddress)

 And usecase example:

 //16k - 32 bit,CAN1

 CAN_6.MCR.B.MDIS = 0x0;
 WRITE_WITH_LOCK_16K_32BIT((&CAN_6.MCR.R), 0xD890000F);
 GET_SOFTLOCK_16K(&CAN_6, &CAN_6.MCR.R,&testik);
 CAN_6.MCR.B.MDIS = 0x0;
 CLR_SOFTLOCK_16K_32BIT(&CAN_6, &CAN_6.MCR.R);
 GET_SOFTLOCK_16K(&CAN_6, &CAN_6.MCR.R,&testik);
 CAN_6.MCR.B.MDIS = 0x0;
 SET_SOFTLOCK_16K_32BIT(&CAN_6, &CAN_6.MCR.R);
 GET_SOFTLOCK_16K(&CAN_6, &CAN_6.MCR.R,&testik);

 //SET_HARDLOCK_16k(&CAN_6);
 CLR_SOFTLOCK_16K_32BIT(&CAN_6, &CAN_6.MCR.R);
 GET_SOFTLOCK_16K(&CAN_6, &CAN_6.MCR.R,&testik);

 CAN_6.MCR.B.MDIS = 0x1;
 USER_ACCESS_FORBIDDEN_16k(&CAN_6);
 GET_GCR_16K(&CAN_6,&GCRvalue);
 CAN_6.MCR.B.MDIS = 0x0;
 USER_ACCESS_ALLOWED_16k(&CAN_6);
 GET_GCR_16K(&CAN_6,&GCRvalue);
 CAN_6.MCR.B.MDIS = 0x0;

 SET_HARDLOCK_16k(&CAN_6);
 GET_GCR_16K(&CAN_6,&GCRvalue);

[Jamber_H]

Hi Peter,

Thank you for your reply. Now I know what the NOTE means, which is a keypoint, and I have had a test, it works well.

Best regards

Jamber

[petervlna]

Hello,

Only registers listed in appendix A can be locked by register protection:

So not all registers in module support this feature. Usually its only safety relevant.

Another question, in the Protected Registers list, why different modules have same Base Address? as shown in the fig.3, CMU0 and CMU1 has a same Base Address 0xFBFB0200, is it correct?

Well, that is copy paste typo in manual, please have a look at manual Addendum instead:

Here are the addresses:

#define CMU_0 (*(volatile struct CMU_tag *) 0xFBFB0200UL)
#define CMU_1 (*(volatile struct CMU_tag *) 0xFBFB0240UL)
#define CMU_2 (*(volatile struct CMU_tag *) 0xFBFB0280UL)
#define CMU_3 (*(volatile struct CMU_tag *) 0xFBFB02C0UL)
#define CMU_4 (*(volatile struct CMU_tag *) 0xFBFB0300UL)

Best regards,

Peter

[Jamber_H]

Hi Peter,

I think I find the answer, but I don't understand. Thanks for your screenshot I saw the NOTE and it said " All CMUs modules are in the same protected region with the base address aligned to the 16k - 0xFBFB_0000", what's the meaning of this?

If the Base Address is 0xFBFB0000, the SoftLock bit should be 0xFBFB0000+0x3800=0xFBFB3800, but this address is still not accseeable as is shown in fig below. So could you tell me how to calculate the CMUs' Mirror Address, SoftLock Address and HardLock Address?

It's so funny different with other modules.

Best regards

Jamber

 

 

[petervlna · Accepted solution]

Hello,

The note is correct.

The base address for all CMUs is 0xFBFB_0000.

f the Base Address is 0xFBFB0000, the SoftLock bit should be 0xFBFB0000+0x3800=0xFBFB3800, but this address is still not accseeable as is shown in fig below. So could you tell me how to calculate the CMUs' Mirror Address, SoftLock Address and HardLock Address?

You calculation is not correct.

You have to take base address of the register: which for 0xFBFB_0200 which is only valid for CMU modules, for other peripherals your base is base address of module.

So for soft locking of CMU0_ CSR register you will do write to 0xFBFB_2200.

And lock register you will see at address 0xFBFB_3880 for CMU0_CSR.

Best regards,

Peter

[Jamber_H]

Hi Peter,

I think it's better understand if modified the value of "Offset" of CMU in Table2-77 to 0x200, 0x208, 0x20C, et.al. but now I get it anyway, thank you.

 

Best Regards

Jamber

[Jamber_H]

Hi Peter, 

Thank you for your reply.

"Only registers listed in appendix A can be locked by register protection:", what confused me is the CMU0 module is right in the Appendix A, but I can't access its SoftLock bit, and I post the screenshot in my question.

Best Regards,

Jamber

[petervlna]

Hmm strange,

I was not aware of this. Trying to think about how to calculate the address.

Let me test it here and I will come back to you ASAP.

best regards,

Peter

[Jamber_H]

Could someone help me please?

[Jamber_H]

I Test MC_ME, CMU, ADC, CTU, PWM, only CMU is failed to set softlock, other modules can set softlock succussfully. Why?