MPC56xx setup Sysclk

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

MPC56xx setup Sysclk

跳至解决方案
2,007 次查看
CCandido
Contributor V

Hi,

I need to modify and Init_pll example, from 40mhz crystal to 20mhz.

see:

/* Set sysclk = 264MHz running from PLL with 40 MHz crystal reference. */
void InitSysclk (void) {
FMPLL.ESYNCR2.R = 0x00000002;
FMPLL.ESYNCR1.R = 0x70040032;
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.ESYNCR2.R = 0x00000001; /* Fsys =264Mhz */
}

//-------

void initCAN_A (void) {
uint8_t i;

CAN_A.MCR.R = 0x5000003F; /* Put in Freeze Mode & enable all 64 message buffers */
CAN_A.CR.R = 0x04ED0002; /* Configure for 40MHz OSC, 500KHz bit time */

//-------------------

TO

my code with Xtal 20mhz, pins PLLCFG[2:0] = 001.

/* Set sysclk = 264/200/180/MHz running from PLL with 20 MHz crystal reference. */ 


void InitSysclk (void) { 
FMPLL.ESYNCR2.R = 0x00000002; 
FMPLL.ESYNCR1.R = 0x10040032;  <----pll = 001
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */ 
FMPLL.ESYNCR2.R = 0x00000001; /* Fsys =264Mhz  or 180/200 Mhz*/ 
}

//-------

void initCAN_A (void) {
CAN_A.MCR.R = 0x5000003F; /* Put in Freeze Mode & enable all 64 message buffers */
CAN_A.CR.R = 0x04ED0002; /* Configure for 20MHz OSC, 500KHz bit time */

-----brabra

thanks,

Carlos.

标签 (1)
标记 (1)
1 解答
1,911 次查看
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Simply use our clock configuration generator and copy the code:

https://community.nxp.com/docs/DOC-332694 

regards,

Peter

在原帖中查看解决方案

1 回复
1,912 次查看
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Simply use our clock configuration generator and copy the code:

https://community.nxp.com/docs/DOC-332694 

regards,

Peter