MPC5674F: clock frequency change

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MPC5674F: clock frequency change

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Contributor I

Hello,

I'm little confused regarding clock configuration and LVDCTRIM register. MPC5674F Microcontroller Reference Manual, Rev. 7, 4.6 Initialization says "When the internal regulator is used to generate 1.2V core supply, it is required to write “1100” to the LVDCTRIM field before clock frequency is increased."

In my understanding there is always an internal regulator used, either SMPS or LDO, depending on REGSEL connection. So it is always necessary to set LVDCTRIM to 1100 before increasing clock frequency?

I've checked multiple NXP examples for MPC5674F, they all increase clock frequency to 264MHz, however LVDCTRIM is always left on default value 1010 and never changed to recommended 1100 before applying new clock frequency. So is it really required to set LVDCTRIM? What are the possible consequences of not doing so?

Thank you in advance!

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NXP TechSupport
NXP TechSupport

Hi, there are certain errors in this chapter. Although documentation tickets has already been created, question is whether new manual revision will be issued for this legacy device.

To your specific question. Right wording in Chapter 4.5.7 is following:

"The assertion and negation voltages are adjustable via software by writing to the LVDCTRIM field of the PMC_TRIMR register, which selects one of the 16 voltages available through the appropriate tapped output. The reset value of the 4-bit register is “1010”, corresponding to the nominal LVD12 voltage.

When an internal regulator (SMPS or LDO) is used to generate the core voltage supply, it is required to change the field of the register to “0110” before increasing core logic clock frequency."

However what the documentation does not say (I think) is that it is quite OK to let default PMC setting as it is. There are different voltage level for SMPS and LDO modes and they are set properly as it should be as well as LVD levels.

Increasing of clock frequency is an operation causing higher current spike what potentially could lead in LVD event in case customer already performed certain "opimization" of PMC setting. That's why customer should re-set LVD level to have higher margin to let regulator to drop to lower level for a while without resetting of the device.

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NXP TechSupport
NXP TechSupport

Hi, there are certain errors in this chapter. Although documentation tickets has already been created, question is whether new manual revision will be issued for this legacy device.

To your specific question. Right wording in Chapter 4.5.7 is following:

"The assertion and negation voltages are adjustable via software by writing to the LVDCTRIM field of the PMC_TRIMR register, which selects one of the 16 voltages available through the appropriate tapped output. The reset value of the 4-bit register is “1010”, corresponding to the nominal LVD12 voltage.

When an internal regulator (SMPS or LDO) is used to generate the core voltage supply, it is required to change the field of the register to “0110” before increasing core logic clock frequency."

However what the documentation does not say (I think) is that it is quite OK to let default PMC setting as it is. There are different voltage level for SMPS and LDO modes and they are set properly as it should be as well as LVD levels.

Increasing of clock frequency is an operation causing higher current spike what potentially could lead in LVD event in case customer already performed certain "opimization" of PMC setting. That's why customer should re-set LVD level to have higher margin to let regulator to drop to lower level for a while without resetting of the device.

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Contributor I

David, thanks for the clarification! I still don't understand the recommended values, could you please help with explanation why are these values recommended and how they work?

Reset configuration of core supply voltage is as follows:

VDDCTRIM = 0b0000 = VDD12OUT = 1.27V

LVDCTRIM = 0b1010 = LVD12           = 1.1V

So far it makes sense for me, low voltage threshold is 0.17V below generated VDD, possible voltage drops will be tolerated without restarting the device.

Recommended values for core supply voltage with internal generator:

VDDCTRIM = 0b1100 = VDD12OUT - 4 * STEPV12 = 1.23V

LVDCTRIM = 0b0110 = LVD12 + 12 * LVDSTEP12   = 1.22V

Now both generated VDD and low voltage threshold are set to almost the same value. Isn't it likely to cause low voltage event, e.g. if clock frequency change would cause current spike? Would it be better to set LVDCTRIM to lowest possible value then?

I've verified how different values for LVDCTRIM work with external core supply and as expected LVDCTRIM level specifies the lowest allowed core supply voltage, i.e. reset occurs if VDD12 drops below the value specified in LVDCTRIM.

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NXP TechSupport
NXP TechSupport

There is an error in the datasheet. Nominal VDD12OUT(LDO) = 1.32V. See discussion below (reported doc ticket):

Q: Do you confirm, that when internal regulator is used, PMC_TRIMR[VDDCTRIM] shall be set to 1100 and that this setting corresponds to nominal 1.23V?

A: No, it is not described clearly.

Actually nominal value of VDD12OUT is different for LDO and SMPS mode –

VDD12OUT(SMPS) = 1.27V

VDD12OUT(LDO) = 1.32V

Recommended VDDCTRIM value to be programmed by user in LDO mode is 0b1100.

For SMPS mode it is recommended to keep nominal level i.e. leave default value of VDDCTRIM (0b0000).

This information will be added to datasheet.

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