MPC5606B LCF file configure

[明伟张]

how to config the LCF file for putting the project code in the special flash address?

for example as follows: the project code is configed at address 0x2000,not 0x8000;

* lcf file for MPC560xB processors */
/* */
/* 1 MB Flash, 80KB SRAM */

MEMORY
{
/*
resetvector: org = 0x00000000, len = 0x00000008
init: org = 0x00000020, len = 0x00000FE0
exception_handlers: org = 0x00001000, len = 0x00001000
internal_flash: org = 0x00002000, len = 0x000FE000

internal_ram: org = 0x40000000, len = 0x00012000
heap : org = 0x40012000, len = 0x00001000
stack : org = 0x40013000, len = 0x00001000
*/

resetvector: org = 0x00000000, len = 0x00000008
APP_ENTRY: org = 0x00008000, len = 0x00078000

init: org = 0x00080020, len = 0x00000FE0
exception_handlers: org = 0x00081000, len = 0x00001000
internal_flash: org = 0x00082000, len = 0x0007E000

internal_ram: org = 0x40000000, len = 0x00006000
heap : org = 0x40006000, len = 0x00001000
stack : org = 0x40007000, len = 0x00001000
}

/* This will ensure the rchw and reset vector are not stripped by the linker */
FORCEACTIVE { "bam_rchw" "bam_resetvector" }

SECTIONS
{
.__bam_bootarea LOAD (0x00000000): {} > resetvector

.app_entry (VLECODE) LOAD(0x00008000) : {} > APP_ENTRY

GROUP : {
.init LOAD (0x00080020) : {}
.init_vle (VLECODE) LOAD (_e_init) : {
*(.init)
*(.init_vle)
}
} > init

GROUP : {
.ivor_branch_table (VLECODE) LOAD (0x00081000) : {}
.__exception_handlers (VLECODE) LOAD (_e_ivor_branch_table) : {}
} > exception_handlers

GROUP : {
.text : {}
.text_vle (VLECODE) ALIGN(0x08): {
*(.text)
*(.text_vle)
}
.rodata (CONST) : {
*(.rdata)
*(.rodata)
}
.ctors : {}
.dtors : {}
extab : {}
extabindex : {}
} > internal_flash

GROUP : {
.__uninitialized_intc_handlertable ALIGN(2048) : {}
.data : {}
.sdata : {}
.sbss : {}
.sdata2 : {}
.sbss2 : {}
.bss : {}
} > internal_ram
}

/* Freescale CodeWarrior compiler address designations */

_stack_addr = ADDR(stack)+SIZEOF(stack);
_stack_end = ADDR(stack);
_heap_addr = ADDR(heap);
_heap_end = ADDR(heap)+SIZEOF(heap);

/* Exceptions Handlers Location (used in Exceptions.c IVPR initialization)*/

EXCEPTION_HANDLERS = ADDR(exception_handlers);

/* L2 SRAM Location (used for L2 SRAM initialization) */

L2SRAM_LOCATION = 0x40000000;

Original Attachment has been moved to: MPC5606B.lcf.zip

[martin_kovar]

Hello,

please look at the linker file code below:

/* lcf file for MPC5604B M27V processors                           */
/*              512KB Flash, 32KB SRAM                                     */

MEMORY
{
    resetvector:           org = 0x00000000,   len = 0x00000008
    init:                   org = 0x00000020,   len = 0x00000FE0    
    exception_handlers:    org = 0x00001000,   len = 0x00001000
    internal_flash:        org = 0x00002000,   len = 0x0007D000
    
    /************************************************************/
    mycode_flash:           org = 0x0007F000,   len = 0x00001000
    /************************************************************/

    internal_ram:          org = 0x40000000,   len = 0x00006000
    heap  :                org = 0x40006000,   len = 0x00001000
    stack :                org = 0x40007000,   len = 0x00001000

}

/* This will ensure the rchw and reset vector are not stripped by the linker */
FORCEACTIVE { "bam_rchw" "bam_resetvector" }

SECTIONS
{
    .__bam_bootarea LOAD (0x00000000): {} > resetvector

    GROUP : {
      .init LOAD (0x00000020) : {}
      .init_vle (VLECODE) LOAD (_e_init) : {
        *(.init)
        *(.init_vle)
      }
    } > init

    GROUP : {
      .ivor_branch_table (VLECODE) LOAD (0x00001000) : {}
      .__exception_handlers  (VLECODE) LOAD (_e_ivor_branch_table) : {}
    } > exception_handlers

    GROUP  : {
      .text : {}
      .text_vle (VLECODE) ALIGN(0x08): {
         *(.text)
         *(.text_vle)
       }
       .rodata (CONST) : {
         *(.rdata)
         *(.rodata)
       }
       .ctors : {}
       .dtors : {}
       extab : {}
       extabindex : {}
    } > internal_flash
    
    /***************************************************************************************/
    GROUP : {
    .mycode (VLECODE) LOAD (0x0007F000) ALIGN (0x1000) : {
        *(.mycode)
        }
    } > mycode_flash

/**********************************************************************************************/

    GROUP : {
       .__uninitialized_intc_handlertable ALIGN(2048) : {}
       .data   : {}
       .sdata  : {}
       .sbss   : {}
       .sdata2 : {}
       .sbss2  : {}
       .bss    : {}
    } > internal_ram
}

/* Freescale CodeWarrior compiler address designations */

_stack_addr = ADDR(stack)+SIZEOF(stack);
_stack_end  = ADDR(stack);
_heap_addr  = ADDR(heap);
_heap_end   = ADDR(heap)+SIZEOF(heap);

/* Exceptions Handlers Location (used in Exceptions.c IVPR initialization)*/

EXCEPTION_HANDLERS    = ADDR(exception_handlers);

/* L2 SRAM Location (used for L2 SRAM initialization) */

L2SRAM_LOCATION = 0x40000000;

and her is code from main.c file:

#pragma push
#pragma section code_type ".mycode"

int8_t fun(volatile int8_t a)
{

a=0;
a=a+1;
return a;
}

#pragma pop

int main(void) {
  volatile int i = 0;
  volatile int8_t a = 10;
     
  fun(a);
 

  /* Loop forever */
  for (;;) {
    i++;
  }
}

If you have any other questions, please feel free to write me back.

Regards,

Martin

[明伟张]

thanks,if do this,I have to write "#pragma push......pragma pop" for all the functions of the project.  I want to configure the LCF file of the APP project for bootloader funtion,can you offer me a sample code app project of mpc5606B?

[martin_kovar]

Hello,

I am not bootloader expert. Please look at the following documents which were created by my colleague who is expert in this area. This examples are not created directly for MPC5606B, but it could be used as a reference design for your application.

https://community.nxp.com/servlet/JiveServlet/download/427962-1-279359/bootloader.zip

http://www.nxp.com/assets/documents/data/en/application-notes/AN5319.pdf

http://www.nxp.com/assets/documents/data/en/application-notes-software/AN5319SW.zip

Hope it helps.

Regards,

Martin