Hi, it does not mean user would have to set up this wait time manually. After starting erase operation application polls MCR[DONE] bit.
However erase time may differ from piece-to-piece and it is also given by aging of flash memory.
Hi David,
as usually:close external interrupts => EHV=1 => waiting for DONE => EHV=0 => open external interrupts;
change :close external interrupts => EHV=1 => open external interrupts=> polls MCR[DONE] => EHV=0;
We need to assess the risk of change
Hi, there is a risk of read-while-write operation in case user software wants to read from the memory during erase/program. It would lead either in bus error or execution stall (according to RWWC, on this device stalls by default).
A solution is to have interrupt vector table and interrupt/exception service routine placed in SRAM.
Yes, you are right. I have somehow forgot we are talking about DFLASH. In case case it should be OK unless interrupt service routine does not access DFLASH.