Hi,
before line 06 - CGM.FMPLL_CR.R = 0x02400100:
/** EXTERNAL CLOCK */
/** Use external clock from crystal oscillator */
/** Use this crystal oscillator in fast mode */
CGM.FXOSC_CTL.B.OSCBYP = 0u;
/** Disable slow mode for external clock */
CGM.SXOSC_CTL.R = 0u;
/** EXTERNAL CLOCK CONTROL */
/** Disable FMPLL clock monitor */
CGM.CMU_CSR.B.CME_A = 0u;
/** Disable frequency measure */
CGM.CMU_CSR.B.SFM = 0u;
/** The external clock shall be greater than FIRC(16MHz)/divisor_value[1, 2, 4, 8]
* Like external clock is between 4 and 16 MHz so divisor_value = 8.
* This condition is always right
*/
CGM.CMU_CSR.B.RCDIV = 3u;
/** PLL COMPUTATION */
/** Disable PLL modulation */
CGM.FMPLL_MR.B.FM_EN = 0u;
then change lines 15 & 16 (check ME.IS) by:
/** wait transition completed */
while (ME.GS.B.S_MTRANS != 0u) {}
/** check clock = 64MHz is stable */
while (ME.GS.B.S_FXOSC != 1u) {}
/** check that current mode = RUN0 */
while (ME.GS.B.S_CURRENTMODE != 4u) {}
Now your clock configuration is right.
Change line 53 by INTC.CPR.R = 0u;
You can toogle pins at each PIT interrupt to ensure that application runs (SIU.PCR[number_pad].R = 0x0200u; /** output GPIO */ before PIT.PITMCR instruction then SIU.GPDO[number_pad].B.PDO = 0/1u; in PitxInterrupt functions /** low / high-level output state */