MPC5604 eMIOS SAOCmode?

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MPC5604 eMIOS SAOCmode?

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1,651件の閲覧回数
binpenghu
Contributor II

hi,all:

i try to use the emios_0 channel18 in  SAOC mode to output a pulse. In the main(),  polling the EMIOS_0.CH[18].CSR.B.FLAG instead of using the interrupt.  but cannot find the FLAG set.

Here is the code:

(1)  how is BUS_ A's clock generated? how to confirm the clock work?                channel 18 has no internal clocks like channel 1-8, so choose the BUS_ A。

(2)  SAOC compared the data stored in the register A1 with internal counter, am i right?   what is the internal clock here?

(3) does the freeze mode matter when i use PE to debug SAOC,  i had disable the freeze mode ,but it didn't help.

emois_0_init()

{

  SIU.PCR[66].R = 0x0603;    //set as emios

 

  EMIOS_0.MCR.B.GPRE  = 63;        // global prescalser set 63

  EMIOS_0.MCR.B.GPREN = 1;         // prescaler enable

  EMIOS_0.MCR.B.GTBE  = 1;         // enable global time base

  EMIOS_0.MCR.B.FRZ   = 0;         // disable the freeze.

 

  EMIOS_0.CH[18].CCR.B.BSL   =  0;        //CLOCK select BUS_ A,

  EMIOS_0.CH[18].CCR.B.EDSEL  = 1;      //troggle

  EMIOS_0.CH[18].CCR.B.UCPRE =  0;      //prescaler set 1

  EMIOS_0.CH[18].CCR.B.UCPEN =  1;      //enable prescaler

  EMIOS_0.CH[18].CCR.B.FREN  =  0;      //disable freeze mode

  EMIOS_0.CH[18].CCR.B.FORCMA = 0;  //

  EMIOS_0.CH[18].CCR.B.FORCMB = 0;  //

  EMIOS_0.CH[18].CCR.B.MODE  =  3;    //select SAOC mode 

 

  EMIOS_0.CH[18].CSR.B.FLAG  = 1;

  EMIOS_0.CH[18].CADR.R=5000;

}

the main:

main:

{

    SWT_DisableWatchDog(); 

    SYSTEM_Init();    //64MHZ

     emois_0_init();

 

// EnableExternalInterrupts();

 

   while(1)

   {

      if(EMIOS_0.CH[18].CSR.B.FLAG  == 1)

      {

      EMIOS_0.CH[18].CSR.B.FLAG  = 1;

      EMIOS_0.CH[18].CADR.R=500;

      }

   };

}

 

thank you very much for your time !!~

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1 解決策
1,419件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

1. Counter bus A is driven by the Unified Channel #23. So you should set the channel 23 to the MCB mode and set the counter boundary by CADR register so the internal counter counts from 1 to CADR value. You can check the CNT register is changed within debugger and also the FLAG is set on match with CADR value.

2. Yes, counter bus in SAOC mode can be either internal or external and is selected through bits BSL[0:1]. The channel’s CNT register represents internal counter bus, but as you wrote the channel 18 (type Y) does not have internal counter implemented, so it cannot work for you. You have to select counter bus A or D (channel 16).

3. When in debug mode, bit FRZ in the EMIOSMCR and bit FREN in the EMIOSC[n] register are both set, the internal counter and Unified Channel capture and compare functions are halted. The UC is frozen in its current state.

BR,

Petr

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3 返答(返信)
1,420件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

1. Counter bus A is driven by the Unified Channel #23. So you should set the channel 23 to the MCB mode and set the counter boundary by CADR register so the internal counter counts from 1 to CADR value. You can check the CNT register is changed within debugger and also the FLAG is set on match with CADR value.

2. Yes, counter bus in SAOC mode can be either internal or external and is selected through bits BSL[0:1]. The channel’s CNT register represents internal counter bus, but as you wrote the channel 18 (type Y) does not have internal counter implemented, so it cannot work for you. You have to select counter bus A or D (channel 16).

3. When in debug mode, bit FRZ in the EMIOSMCR and bit FREN in the EMIOSC[n] register are both set, the internal counter and Unified Channel capture and compare functions are halted. The UC is frozen in its current state.

BR,

Petr

1,419件の閲覧回数
binpenghu
Contributor II

hi Petr Stancik,

thank you for your reply.

(1) if set channel#23 CADR = 500, and the channel#18 CADR =1000, then the channel#18 match event didn't happen? and  if set CHANNEL#23 CADR=1000  and CHANNEL#18 CADR=1000,generate a 2ms cycle square wave. if change the channel#18 CADR value,  #18CADR = 500 and #CADR=1000, would generate the  same 2ms cycle square wave?

EMIOS_0.CH[23].CCR.B.BSL = 0x03; // use internal clock.

EMIOS_0.CH[23].CCR.B.MODE = 0x50; //MCB mode,internal clock input

EMIOS_0.CH[23].CCR.B.UCPEN = 1;

EMIOS_0.CH[23].CCR.B.UCPRE = 0;

EMIOS_0.CH[23].CADR.R = 500;

in the main:

   while(1)

   {

   if(EMIOS_0.CH[18].CSR.B.FLAG  == 1)

   {

       EMIOS_0.CH[18].CSR.B.FLAG  = 1;

       EMIOS_0.CH[18].CADR.R=500;

        LED1 = ~LED1;

   }

   };

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返信
1,419件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

The channel CADR must be less or equal to external bus CADR register otherwise the FLAG is not set and output is not toggled.

So if CHANNEL#23 CADR=1000  and CHANNEL#18 CADR=1000 then the FLAG is set each 1ms. In your code you will see 2ms square wave on the LED. The same will be if you will use  CHANNEL#23 CADR=1000  and CHANNEL#18 CADR=500.

BTW if using SAOC mode you can see square wave directly on the eMIOS output.

BR,

Petr