Hello,
when i use IPWM module, with the 25% input pulse, the capture pulse width sometimes is 75% or otherwise 25%.
How could this happen? What can i do about it?
Hi,
This should not happen if the reading of A[n] register is followed by B[n] reading, this always provides coherent data.
Or the counter bus overflow happens and pulse width is not properly calculated.
BR, Petr
